diff options
| author | Alan Lawrence <alan.lawrence@arm.com> | 2015-09-08 19:24:35 +0000 |
|---|---|---|
| committer | Alan Lawrence <alalaw01@gcc.gnu.org> | 2015-09-08 19:24:35 +0000 |
| commit | 03873eb98330b17e73ada713f31bcbcd50d74026 (patch) | |
| tree | d98f7ca7a0157c1fa28bdf8b91d634d68db2be05 /gcc/config/aarch64/iterators.md | |
| parent | 862abc04beb0874f2e4352c44f28849a52c5c434 (diff) | |
| download | gcc-03873eb98330b17e73ada713f31bcbcd50d74026.zip gcc-03873eb98330b17e73ada713f31bcbcd50d74026.tar.gz gcc-03873eb98330b17e73ada713f31bcbcd50d74026.tar.bz2 | |
[AArch64] Add vcvt(_high)?_f32_f16 intrinsics, with BE RTL fix
gcc/:
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_<mode>,
aarch64_simd_vec_unpacks_hi_<mode>): New insn.
(vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn.
(vec_unpacks_lo_<mode>, vec_unpacks_hi_<mode>): New expand.
(aarch64_float_extend_lo_v2df): Rename to...
(aarch64_float_extend_lo_<Vwide>): this, using VDF and so adding V4SF.
* config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf.
(float_extend_lo): Add v4sf.
* config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New.
* config/aarch64/iterators.md (VQ_HSF): New iterator.
(VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF.
(Vwide): New mode_attr.
From-SVN: r227551
Diffstat (limited to 'gcc/config/aarch64/iterators.md')
| -rw-r--r-- | gcc/config/aarch64/iterators.md | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 0210602..2bd64c8 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -94,6 +94,9 @@ ;; Vector single Float modes. (define_mode_iterator VDQSF [V2SF V4SF]) +;; Quad vector Float modes with half/single elements. +(define_mode_iterator VQ_HSF [V8HF V4SF]) + ;; Modes suitable to use as the return type of a vcond expression. (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI]) @@ -492,14 +495,18 @@ (V2SI "V2DI") (V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI") (HI "SI") (SI "DI") + (V8HF "V4SF") (V4SF "V2DF") (V4HF "V4SF") (V2SF "V2DF")] - ) -;; Widened mode register suffixes for VD_BHSI/VQW. +;; Widened modes of vector modes, lowercase +(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")]) + +;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF. (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s") (V2SI "2d") (V16QI "8h") - (V8HI "4s") (V4SI "2d")]) + (V8HI "4s") (V4SI "2d") + (V8HF "4s") (V4SF "2d")]) ;; Widened mode register suffixes for VDW/VQW. (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s") @@ -508,9 +515,10 @@ (V4HF ".4s") (V2SF ".2d") (SI "") (HI "")]) -;; Lower part register suffixes for VQW. +;; Lower part register suffixes for VQW/VQ_HSF. (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h") - (V4SI "2s")]) + (V4SI "2s") (V8HF "4h") + (V4SF "2s")]) ;; Define corresponding core/FP element mode for each vector mode. (define_mode_attr vw [(V8QI "w") (V16QI "w") |