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path: root/gcc/config/aarch64/iterators.md
AgeCommit message (Expand)AuthorFilesLines
3 daysaarch64: Fix bug with max/min (PR116934)Saurabh Jha1-4/+4
6 daysaarch64: Introduce new unspecs for smax/sminSaurabh Jha1-28/+45
14 daysaarch64: Add codegen support for AdvSIMD faminmaxSaurabh Jha1-0/+3
14 daysaarch64: Add AdvSIMD faminmax intrinsicsSaurabh Jha1-0/+9
2024-08-08AArch64: Fix signbit mask creation after late combine [PR116229]Tamar Christina1-0/+1
2024-08-01aarch64: Improve Advanced SIMD popcount expansion by using SVE [PR113860]Pengxuan Zheng1-0/+5
2024-07-24aarch64: Add bool conversion to TARGET_* macrosAndrew Carlotti1-2/+2
2024-06-12aarch64: Use bitreverse rtl code instead of unspec [PR115176]Andrew Pinski1-5/+5
2024-01-24AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]Tamar Christina1-4/+15
2024-01-12aarch64: Rework uxtl->zip optimisation [PR113196]Richard Sandiford1-0/+2
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-15aarch64: Rewrite non-writeback ldp/stp patternsAlex Coplan1-0/+3
2023-12-13aarch64: SVE/NEON Bridging intrinsicsRichard Ball1-0/+1
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-0/+12
2023-12-07aarch64: rcpc3: Add relevant iterators to handle Neon intrinsicsVictor Do Nascimento1-8/+17
2023-12-05aarch64: Add support for SME2 intrinsicsRichard Sandiford1-15/+354
2023-12-05aarch64: Add support for <arm_sme.h>Richard Sandiford1-3/+91
2023-12-05aarch64: Mark relevant SVE instructions as non-streamingRichard Sandiford1-2/+2
2023-12-05aarch64: Add tuple forms of svreinterpretRichard Sandiford1-8/+18
2023-11-22AArch64: fix aarch64_usubw patternTamar Christina1-7/+1
2023-11-21AArch64: Add pattern for unsigned widenings (uxtl) to zip{1,2}Tamar Christina1-1/+7
2023-11-10Allow md iterators to include other iteratorsRichard Sandiford1-45/+15
2023-11-09AArch64: Add movi for 0 moves for scalar types [PR109154]Tamar Christina1-0/+1
2023-10-19aarch64: Generalise TFmode load/store pair patternsAlex Coplan1-0/+3
2023-10-02AArch64: Fix scalar xorsign loweringTamar Christina1-1/+2
2023-06-30AArch64: New RTL for ABDLOluwatamilore Adebayo1-0/+3
2023-06-16aarch64: [US]Q(R)SHR(U)N2 refactoringKyrylo Tkachov1-19/+0
2023-06-16aarch64: Add ASHIFTRT handling for shrn patternKyrylo Tkachov1-0/+2
2023-06-16aarch64: [US]Q(R)SHR(U)N scalar forms refactoringKyrylo Tkachov1-1/+2
2023-06-16aarch64: Reimplement [US]Q(R)SHR(U)N patterns with RTL codesKyrylo Tkachov1-0/+12
2023-06-07aarch64: Represent SQXTUN with RTL operationsKyrylo Tkachov1-1/+2
2023-06-06aarch64: Improve representation of ADDLV instructionsKyrylo Tkachov1-6/+6
2023-05-30aarch64: Convert ADDLP and ADALP patterns to standard RTL codesKyrylo Tkachov1-9/+0
2023-05-30stor-layout, aarch64: Express SRA intrinsics with RTL codesKyrylo Tkachov1-5/+13
2023-05-23aarch64: Provide FPR alternatives for some bit insertions [PR109632]Richard Sandiford1-0/+4
2023-05-04[2/2] aarch64: Reimplement (R){ADD,SUB}HN2 patterns with standard RTL codesKyrylo Tkachov1-14/+1
2023-04-25aarch64: Implement V2DI,V4SI division optabs for TARGET_SVEKyrylo Tkachov1-0/+5
2023-04-25aarch64: Leveraging the use of STP instruction for vec_duplicateVictor Do Nascimento1-0/+3
2023-04-24[4/4] aarch64: Convert UABAL2 and SABAL2 patterns to standard RTL codesKyrylo Tkachov1-4/+0
2023-04-24[3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codesKyrylo Tkachov1-4/+0
2023-04-24[2/4] aarch64: Convert UABDL2 and SABDL2 patterns to standard RTL codesKyrylo Tkachov1-4/+0
2023-04-24[1/4] aarch64: Convert UABDL and SABDL patterns to standard RTL codesKyrylo Tkachov1-4/+0
2023-04-21aarch64: Emit single-instruction for smin (x, 0) and smax (x, 0)Kyrylo Tkachov1-0/+2
2023-04-21aarch64: PR target/99195 Add scheme to optimise away vec_concat with zeroes o...Kyrylo Tkachov1-0/+3
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2023-01-06Revert "aarch64: Make existing V2HF be usable."Tamar Christina1-21/+9
2022-12-12AArch64: Support new tbranch optab.Tamar Christina1-0/+2
2022-12-12aarch64: Make existing V2HF be usable.Tamar Christina1-9/+21
2022-11-18aarch64: Fix LDAPURS assembly outputKyrylo Tkachov1-4/+0
2022-11-18aarch64: Fix up LDAPR codegenKyrylo Tkachov1-0/+4
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