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path: root/gcc/config/aarch64/aarch64-sve.md
AgeCommit message (Expand)AuthorFilesLines
14 daysaarch64: Emit ADD X, Y, Y instead of SHL X, Y, #1 for SVE instructions.Soumya AR1-3/+15
2024-08-01aarch64: Improve Advanced SIMD popcount expansion by using SVE [PR113860]Pengxuan Zheng1-6/+7
2024-07-26aarch64: sve: Rename aarch64_bic to standard pattern, andnAndrew Pinski1-2/+2
2024-06-12aarch64: Use bitreverse rtl code instead of unspec [PR115176]Andrew Pinski1-1/+1
2024-06-06AArch64: correct constraint on Upl early clobber alternativesTamar Christina1-32/+32
2024-06-05AArch64: add new alternative with early clobber to patternsTamar Christina1-58/+120
2024-06-05AArch64: convert several predicate patterns to new compact syntaxTamar Christina1-108/+154
2024-04-05aarch64: Fix bogus cnot optimisation [PR114603]Richard Sandiford1-11/+11
2024-01-24AArch64: Fix expansion of Advanced SIMD div and mul using SVE [PR109636]Tamar Christina1-29/+51
2024-01-03Update copyright years.Jakub Jelinek1-1/+1
2023-12-15aarch64: Handle autoinc addresses in ld1rq splitter [PR112906]Alex Coplan1-4/+1
2023-12-13aarch64: SVE/NEON Bridging intrinsicsRichard Ball1-0/+33
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford1-44/+0
2023-12-05aarch64: Add support for SME2 intrinsicsRichard Sandiford1-19/+79
2023-12-05aarch64: Add svboolx2_tRichard Sandiford1-0/+22
2023-12-05aarch64: Mark relevant SVE instructions as non-streamingRichard Sandiford1-56/+68
2023-12-05aarch64: Add tuple forms of svreinterpretRichard Sandiford1-4/+4
2023-11-09AArch64: Add SVE implementation for cond_copysign.Tamar Christina1-0/+51
2023-11-09AArch64: Handle copysign (x, -1) expansion efficientlyTamar Christina1-6/+21
2023-10-03aarch64: Convert aarch64 multi choice patterns to new syntaxAndrea Corallo1-1459/+1514
2023-09-14aarch64: Coerce addresses to be suitable for LD1RQRichard Sandiford1-1/+14
2023-06-21aarch64: Avoid same input and output Z register for gather loadsKyrylo Tkachov1-67/+127
2023-06-21aarch64: Convert SVE gather patterns to compact syntaxKyrylo Tkachov1-176/+194
2023-06-21Revert "aarch64: Convert SVE gather patterns to compact syntax"Kyrylo Tkachov1-254/+176
2023-06-21aarch64: Convert SVE gather patterns to compact syntaxKyrylo Tkachov1-176/+254
2023-06-15AArch64: New RTL for ABDOluwatamilore Adebayo1-2/+2
2023-05-09aarch64: Improve register allocation for lane instructionsRichard Sandiford1-1/+1
2023-04-24aarch64: PR target/109406 Add support for SVE2 unpredicated MULKyrylo Tkachov1-0/+9
2023-04-24[3/4] aarch64: Convert UABAL and SABAL patterns to standard RTL codesKyrylo Tkachov1-4/+4
2023-01-16Update copyright years.Jakub Jelinek1-1/+1
2023-01-14[aarch64] Fold ldr+dup to ld1rq for little endian targets.Prathamesh Kulkarni1-5/+25
2022-10-20aarch64: Prevent generation of /M BRKAS and BRKBSRichard Sandiford1-14/+10
2022-10-20aarch64: Fix matching of BRKNSRichard Sandiford1-8/+62
2022-08-12sve: Fix fcmuo combine patterns [PR106524]Tamar Christina1-2/+2
2022-02-02AArch64: use canonical ordering for complex mul, fma and fmsTamar Christina1-3/+3
2022-01-03Update copyright years.Jakub Jelinek1-1/+1
2021-11-30vect: Add support for fmax and fmin reductionsRichard Sandiford1-0/+11
2021-11-17Add IFN_COND_FMIN/FMAX functionsRichard Sandiford1-1/+18
2021-11-10aarch64: Tweak FMAX/FMIN iteratorsRichard Sandiford1-1/+1
2021-10-12sve: combine inverted masks into NOTsTamar Christina1-0/+154
2021-07-14AArch64: Add support for sign differing dot-product usdot for NEON and SVE.Tamar Christina1-1/+1
2021-05-19aarch64: Enable aarch64_load to use UNSPEC_PRED_X loadsAndre Simoes Dias Vieira1-2/+2
2021-04-16SVE: Fix wrong sve predicate split (PR100048)Tamar Christina1-0/+14
2021-02-19aarch64: Check predicate when using gen_vec_duplicate [PR98657]Andre Vieira1-4/+2
2021-01-15AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, FMS and FMA.Tamar Christina1-0/+56
2021-01-13aarch64: Add support for unpacked SVE MLS and MSBRichard Sandiford1-44/+44
2021-01-13aarch64: Add support for unpacked SVE MLA and MADRichard Sandiford1-44/+44
2021-01-11aarch64: Add support for unpacked SVE ASRDRichard Sandiford1-38/+81
2021-01-11aarch64: Add support for unpacked SVE conditional BICRichard Sandiford1-13/+13
2021-01-11aarch64: Add support for unpacked SVE MULHRichard Sandiford1-10/+10
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