aboutsummaryrefslogtreecommitdiff
path: root/gcc/config/aarch64/aarch64-simd.md
AgeCommit message (Expand)AuthorFilesLines
2017-08-31[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>James Greenhalgh1-2/+2
2017-08-31[AArch64] Rename cmp_result iteratorRichard Sandiford1-61/+61
2017-08-31[AArch64] Remove use of wider vector modesRichard Sandiford1-252/+31
2017-08-17[AArch64] Improve SIMD store of zero.Jackson Woodruff1-22/+28
2017-08-08re PR middle-end/19706 (Recognize common Fortran usages of copysign.)Tamar Christina1-0/+29
2017-08-01re PR target/80846 (auto-vectorized AVX2 horizontal sum should narrow to 128b...Jakub Jelinek1-4/+4
2017-07-24[AArch64, Patch] Generate MLA when multiply + add vector by scalarJackson Woodruff1-0/+24
2017-06-27aarch64-simd.md (aarch64_combine<mode>): Directly call aarch64_split_simd_com...Michael Collison1-29/+1
2017-06-21Emit SIMD moves as movWilco Dijkstra1-2/+2
2017-06-21Improve dup patternWilco Dijkstra1-4/+4
2017-06-21* config/aarch64/aarch64-simd.md (aarch64_crypto_pmulldi)Julian Brown1-2/+2
2017-06-05[AArch64] Add combine pattern for storing lane zero of a vectorKyrylo Tkachov1-0/+13
2017-06-02[AArch64] Add HF vector modes to lane-to-lane INS patternKyrylo Tkachov1-5/+5
2017-04-25aarch64-simd.md (aarch64_simd_vec_set<mode>): Fix type for 1-element load.Julian Brown1-1/+1
2017-03-162017-03-16 Tamar Christina <tamar.christina@arm.com>Tamar Christina1-3/+3
2017-03-16[AArch64] Use 'x' constraint for vector HFmode multiplication by indexed elem...Kyrylo Tkachov1-3/+3
2017-03-09[AArch64] PR target/79913: VEC_SELECT bugs in aarch64 patternsKyrylo Tkachov1-7/+7
2017-01-19aarch64.c (aarch64_simd_gen_const_vector_dup): Change int to HOST_WIDE_INT.Tamar Christina1-0/+18
2017-01-01Update copyright years.Jakub Jelinek1-1/+1
2016-11-02Add LE/BE SHA1H patterns with a V2SI input.Wilco Dijkstra1-0/+20
2016-09-30* config/aarch64/aarch64-simd.md: Adjust fall through comments.Marek Polacek1-2/+2
2016-08-30[PATCH][Aarch64][gcc] Fix vld2/3/4 on big endian systemsTamar Christina1-16/+159
2016-08-16re PR tree-optimization/69848 (poor vectorization of a loop from SPEC2006 464...Bin Cheng1-0/+40
2016-08-11aarch64-simd.md (vcond<mode><mode>): Delete unused declaration.Bin Cheng1-4/+0
2016-08-11aarch64-simd.md (vec_cmp<mode><v_cmp_result>): Init variable explicitly, also...Bin Cheng1-1/+3
2016-08-10iterators.md (V_cmp_mixed, [...]): New.Bin Cheng1-326/+53
2016-08-10aarch64-simd.md (vec_cmp<mode><mode>): New pattern.Alan Lawrence1-0/+269
2016-08-02[PATCH AArch64] Add more AArch64 NEON intrinsicsTamar Christina1-11/+3
2016-07-25[AArch64][8/10] ARMv8.2-A FP16 two operands scalar intrinsicsJiong Wang1-20/+20
2016-07-25[AArch64][7/10] ARMv8.2-A FP16 one operand scalar intrinsicsJiong Wang1-8/+34
2016-07-25[AArch64][6/14] ARMv8.2-A FP16 reduction vector intrinsicsJiong Wang1-6/+6
2016-07-25[AArch64][5/10] ARMv8.2-A FP16 lane vector intrinsicsJiong Wang1-15/+13
2016-07-25[AArch64][4/10] ARMv8.2-A FP16 three operands vector intrinsicsJiong Wang1-14/+14
2016-07-25[AArch64][3/10] ARMv8.2-A FP16 two operands vector intrinsicsJiong Wang1-77/+83
2016-07-25[AArch64][2/10] ARMv8.2-A FP16 one operand vector intrinsicsJiong Wang1-42/+42
2016-07-25[AArch64][1/10] ARMv8.2-A FP16 data processing intrinsicsJiong Wang1-11/+11
2016-06-30[AArch64][1/2] Add support INS (element) instruction to copy lanes between ve...James Greenhalgh1-0/+43
2016-06-15[AArch64][obvious] Clean up parentheses and use GET_MODE_UNIT_BITSIZE in a co...Kyrylo Tkachov1-14/+8
2016-06-13[AArch64] Emit division using the Newton seriesEvandro Menezes1-1/+13
2016-06-13[AArch64] Emit square root using the Newton seriesEvandro Menezes1-2/+11
2016-06-08[AArch64, 6/6] Reimplement vpadd intrinsics & extend rtl patterns to all modesJiong Wang1-11/+12
2016-06-08[AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patternsJiong Wang1-16/+7
2016-06-08[AArch64, 4/6] Reimplement frsqrts intrinsicsJiong Wang1-1/+1
2016-06-08[AArch64, 3/6] Reimplement frsqrte intrinsicsJiong Wang1-1/+1
2016-06-08[AArch64, 2/6] Reimplement vector fixed-point intrinsicsJiong Wang1-0/+22
2016-05-31[AArch64] Remove aarch64_simd_attr_length_moveKyrylo Tkachov1-4/+4
2016-05-27[AArch64] Tie operand 1 to operand 0 in AESMC pattern when AES/AESMC fusion i...Kyrylo Tkachov1-3/+15
2016-05-26SIMD operations like combine prefer to have their operands in FP registers,Wilco Dijkstra1-2/+2
2016-05-18[Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequenceJames Greenhalgh1-16/+3
2016-05-17[AArch64, 2/4] Extend vector mutiply by element to all supported modesJiong Wang1-8/+8
generated by cgit v1.1 at 2025-02-06 05:25:22 +0000