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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2016-05-18 08:00:33 +0000 |
|---|---|---|
| committer | James Greenhalgh <jgreenhalgh@gcc.gnu.org> | 2016-05-18 08:00:33 +0000 |
| commit | 628d13d9995e6b1d2c0847106ebf2645b3884875 (patch) | |
| tree | e1d3be451e722fa96a9caee48dc050914ba061e9 /gcc/config/aarch64/aarch64-simd.md | |
| parent | f38748638a7de7e10884f68f89b4f660cd15fecc (diff) | |
| download | gcc-628d13d9995e6b1d2c0847106ebf2645b3884875.zip gcc-628d13d9995e6b1d2c0847106ebf2645b3884875.tar.gz gcc-628d13d9995e6b1d2c0847106ebf2645b3884875.tar.bz2 | |
[Patch AArch64] Simplify reduc_plus_scal_v2[sd]f sequence
gcc/
* config/aarch64/aarch64-simd.md
(aarch64_reduc_plus_internal<mode>): Rename to...
(reduc_plus_scal): ...This, and remove previous implementation.
From-SVN: r236360
Diffstat (limited to 'gcc/config/aarch64/aarch64-simd.md')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 19 |
1 files changed, 3 insertions, 16 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 17b8945..59a578f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1979,19 +1979,6 @@ } ) -(define_expand "reduc_plus_scal_<mode>" - [(match_operand:<VEL> 0 "register_operand" "=w") - (match_operand:V2F 1 "register_operand" "w")] - "TARGET_SIMD" - { - rtx elt = GEN_INT (ENDIAN_LANE_N (<MODE>mode, 0)); - rtx scratch = gen_reg_rtx (<MODE>mode); - emit_insn (gen_aarch64_reduc_plus_internal<mode> (scratch, operands[1])); - emit_insn (gen_aarch64_get_lane<mode> (operands[0], scratch, elt)); - DONE; - } -) - (define_insn "aarch64_reduc_plus_internal<mode>" [(set (match_operand:VDQV 0 "register_operand" "=w") (unspec:VDQV [(match_operand:VDQV 1 "register_operand" "w")] @@ -2010,9 +1997,9 @@ [(set_attr "type" "neon_reduc_add")] ) -(define_insn "aarch64_reduc_plus_internal<mode>" - [(set (match_operand:V2F 0 "register_operand" "=w") - (unspec:V2F [(match_operand:V2F 1 "register_operand" "w")] +(define_insn "reduc_plus_scal_<mode>" + [(set (match_operand:<VEL> 0 "register_operand" "=w") + (unspec:<VEL> [(match_operand:V2F 1 "register_operand" "w")] UNSPEC_FADDV))] "TARGET_SIMD" "faddp\\t%<Vetype>0, %1.<Vtype>" |