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| author | Tamar Christina <tamar.christina@arm.com> | 2017-08-08 13:17:41 +0000 |
|---|---|---|
| committer | Tamar Christina <tnfchris@gcc.gnu.org> | 2017-08-08 13:17:41 +0000 |
| commit | 4261463d962c29bc105f973a8ab4269cf566cd1b (patch) | |
| tree | 585e331e9be3be86535e1e88262394af21fa11f6 /gcc/config/aarch64/aarch64-simd.md | |
| parent | 336a06a163f7a761f7c3b223a1dd9a1b81cda2cb (diff) | |
| download | gcc-4261463d962c29bc105f973a8ab4269cf566cd1b.zip gcc-4261463d962c29bc105f973a8ab4269cf566cd1b.tar.gz gcc-4261463d962c29bc105f973a8ab4269cf566cd1b.tar.bz2 | |
re PR middle-end/19706 (Recognize common Fortran usages of copysign.)
2017-08-08 Tamar Christina <tamar.christina@arm.com>
PR middle-end/19706
* config/aarch64/aarch64.md (xorsign<mode>3): New optabs.
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Added CASE_CFN_XORSIGN.
* config/aarch64/aarch64-simd-builtins.def: Added xorsign BINOP.
* config/aarch64/aarch64-simd.md: Added xorsign<mode>3.
gcc/testsuite/
2017-08-08 Tamar Christina <tamar.christina@arm.com>
* gcc.target/aarch64/xorsign.c: New.
* gcc.target/aarch64/xorsign_exec.c: New.
* gcc.target/aarch64/vect-xorsign_exec.c: New.
From-SVN: r250957
Diffstat (limited to 'gcc/config/aarch64/aarch64-simd.md')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 74de9b8..f74b687 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -351,6 +351,35 @@ } ) +(define_expand "xorsign<mode>3" + [(match_operand:VHSDF 0 "register_operand") + (match_operand:VHSDF 1 "register_operand") + (match_operand:VHSDF 2 "register_operand")] + "TARGET_SIMD" +{ + + machine_mode imode = <V_cmp_result>mode; + rtx v_bitmask = gen_reg_rtx (imode); + rtx op1x = gen_reg_rtx (imode); + rtx op2x = gen_reg_rtx (imode); + + rtx arg1 = lowpart_subreg (imode, operands[1], <MODE>mode); + rtx arg2 = lowpart_subreg (imode, operands[2], <MODE>mode); + + int bits = GET_MODE_UNIT_BITSIZE (<MODE>mode) - 1; + + emit_move_insn (v_bitmask, + aarch64_simd_gen_const_vector_dup (<V_cmp_result>mode, + HOST_WIDE_INT_M1U << bits)); + + emit_insn (gen_and<v_cmp_result>3 (op2x, v_bitmask, arg2)); + emit_insn (gen_xor<v_cmp_result>3 (op1x, arg1, op2x)); + emit_move_insn (operands[0], + lowpart_subreg (<MODE>mode, op1x, imode)); + DONE; +} +) + (define_expand "copysign<mode>3" [(match_operand:VHSDF 0 "register_operand") (match_operand:VHSDF 1 "register_operand") |