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2024-09-27i386: Modernize AMD processor typesUros Bizjak1-35/+11
2024-09-06AVR: Remove "Atmel" from header comment.Georg-Johann Lay1-1/+1
2024-09-06RISC-V: Fix out of index in riscv_select_multilib_by_abiYunQiang Su1-1/+1
2024-09-05RISC-V: Lookup reversely in riscv_select_multilib_by_abiYunQiang Su1-1/+1
2024-08-12Initial support for AVX10.2Haochen Jiang4-2/+52
2024-08-08RISC-V: Minimal support for Zimop extension.Jiawei1-0/+8
2024-07-31pru: Enable section anchoring by defaultDimitar Dimitrov1-0/+12
2024-07-30RISC-V: Add configure check for B extention supportEdwin Lu1-0/+8
2024-07-30RISC-V: Add basic support for the Zacas extensionGianluca Guida1-0/+3
2024-07-30RISC-V: Remove configure check for zabhaPatrick O'Neill1-9/+3
2024-07-24aarch64: Extend aarch64_feature_flags to 128 bitsAndrew Carlotti1-4/+8
2024-07-24aarch64: Decouple feature flag option storage typeAndrew Carlotti1-5/+6
2024-07-24aarch64: Define aarch64_get_{asm_|}isa_flagsAndrew Carlotti1-1/+1
2024-07-15RISC-V: Allow adding enabled extension via target arch attributesChristoph Müllner1-6/+11
2024-07-15RISC-V: Rewrite target attribute handlingChristoph Müllner1-109/+4
2024-07-12RISC-V: Add SiFive extensions, xsfvcp and xsfceaseKito Cheng1-0/+8
2024-07-11RISC-V: c implies zca, and conditionally zcf & zcdFei Gao1-0/+12
2024-07-10RISC-V: Add support for B standard extensionEdwin Lu1-0/+7
2024-07-09RISC-V: Deduplicate arch subset list processingChristoph Müllner1-26/+6
2024-07-09i386: Correct AVX10 CPUID emulationHaochen Jiang1-2/+2
2024-07-08[RISC-V] add implied extension repeatly until stableFei Gao1-3/+11
2024-07-03RISC-V: Add support for Zabha extensionGianluca Guida1-0/+12
2024-06-19RISC-V: Promote Zaamo/Zalrsc to a when using an old binutilsPatrick O'Neill1-0/+1
2024-06-19i386: Zhaoxin shijidadao enablementmayshao3-3/+14
2024-06-17RISC-V: Add configure check for Zaamo/Zalrsc assembler supportPatrick O'Neill1-0/+11
2024-06-11RISC-V: Add basic Zaamo and Zalrsc supportEdwin Lu1-2/+9
2024-06-03Add AVX10.1 target_clones supportHaochen Jiang3-5/+8
2024-05-20i386: Remove Xeon Phi ISA supportHaochen Jiang4-134/+5
2024-05-16RISC-V: Add Zvfbfwma extension to the -march= optionXiao Zeng1-0/+5
2024-05-06[PATCH 1/1] RISC-V: Add Zfbfmin extension to the -march= optionXiao Zeng1-0/+3
2024-04-29RISC-V: Fix parsing of Zic* extensionsChristoph Müllner1-4/+4
2024-04-22i386: Fix Sierra Forest auto dispatchHaochen Jiang1-1/+1
2024-03-31RISC-V: Fix one unused varable in riscv_subset_list::parsePan Li1-1/+0
2024-03-22RISC-V: Bugfix function target attribute pollutionPan Li1-2/+103
2024-03-22RISC-V: Bugfix ICE for __attribute__((target("arch=+v"))Pan Li1-10/+21
2024-03-18[PATCH v5 1/1] RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+2
2024-03-18Add AMD znver5 processor enablement with scheduler modelJan Hubicka3-1/+23
2024-02-29AVR: target/114100 - Better indirect accesses for reduced TinyGeorg-Johann Lay1-0/+2
2024-02-16RISC-V: Add new option -march=help to print all supported extensionsKito Cheng1-0/+46
2024-02-01RISC-V: Add minimal support for 7 new unprivileged extensionsMonk Chiang1-0/+14
2024-01-25RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett1-0/+2
2024-01-24RISC-V: Don't make Ztso imply APalmer Dabbelt1-2/+0
2024-01-19RISC-V: Add the Zihpm and Zicntr extensionsPalmer Dabbelt1-0/+3
2024-01-19RISC-V: Remove unused function in riscv_subset_list [NFC]Kito Cheng1-179/+0
2024-01-19RISC-V: Relax the -march string for accept any orderKito Cheng1-37/+54
2024-01-19RISC-V: Extract part parsing base ISA logic into a standalone function [NFC]Kito Cheng1-24/+45
2024-01-18RISC-V: Introduce XTheadVector as a subset of V1.0.0Jun Sha (Joshua)1-0/+23
2024-01-03Update copyright years.Jakub Jelinek56-56/+56
2023-12-16[aarch64] Add function multiversioning supportAndrew Carlotti1-0/+94
2023-12-16aarch64: Fix +nopredres, +nols64 and +nomopsAndrew Carlotti1-8/+3