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AgeCommit message (Expand)AuthorFilesLines
2023-02-12RISC-V: Add vmulh C/C++ supportJu-Zhe Zhong1-0/+1
2023-02-09i386: Call get_available_features for all CPUs with max_level >= 1 [PR100758]Jakub Jelinek1-16/+9
2023-02-02RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv.Jin Ma1-1/+4
2023-02-01AArch64: Fix native detection in the presence of mandatory features which don...Tamar Christina1-5/+17
2023-01-30riscv: Enable -fasynchronous-unwind-tables by default on LinuxAndreas Schwab1-0/+4
2023-01-23[PATCH 1/15] arm: Make mbranch-protection opts parsing common to AArch32/64Andrea Corallo1-6/+7
2023-01-16Update copyright years.Jakub Jelinek55-55/+55
2023-01-13arm: Add cde feature support for Cortex-M55 CPU.Srinath Parvathaneni1-9/+12
2023-01-05Add AMD znver4 instruction reservationsTejas Joshi1-1/+1
2023-01-04Initial Emeraldrapids SupportHu, Lin12-0/+4
2023-01-04i386: Remove Meteorlake's family_modelHu, Lin11-1/+0
2022-12-27Fixed typo in RISCVjinma1-1/+1
2022-12-27rs6000: Rework option -mpowerpc64 handling [PR106680]Kewen Lin1-11/+0
2022-11-24i386: Only enable small loop unrolling in backend [PR 107692]Hongyu Wang1-0/+8
2022-11-14Revert "sphinx: port .def files to RST"Martin Liska1-14/+14
2022-11-14i386: Add AMX-TILE dependency for AMX related ISAsHaochen Jiang1-4/+9
2022-11-14Enable small loop unrolling for O2Hongyu Wang1-0/+1
2022-11-09sphinx: port .def files to RSTMartin Liska1-14/+14
2022-11-07Initial Grand Ridge supportHu, Lin13-0/+10
2022-11-07Support Intel RAO-INTkonglin14-0/+19
2022-11-07Initial Granite Rapids SupportHaochen Jiang3-0/+13
2022-11-07Support Intel prefetchit0/t1Haochen Jiang4-0/+19
2022-11-04Support Intel AMX-FP16 ISAHongyu Wang4-0/+22
2022-11-04Initial Sierra Forest SupportHaochen Jiang3-0/+10
2022-11-04Support Intel CMPccXADDHaochen Jiang4-0/+19
2022-11-02RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+4
2022-10-31Support Intel AVX-NE-CONVERTkonglin14-1/+25
2022-10-27RISC-V: Minimal support of z*inx extension.Jiawei1-0/+18
2022-10-26i386: add reset_cpu_featureMartin Liska1-5/+33
2022-10-26RISC-V: Recognized Svinval and Svnapot extensionsMonk Chiang1-0/+6
2022-10-26RISC-V: Add h extension supportKito Cheng1-15/+8
2022-10-25Remove znver4 instruction reservationsTejas Joshi1-1/+1
2022-10-25riscv: fix cross compilerMartin Liska1-4/+4
2022-10-25i386: fix pedantic warningMartin Liska1-1/+1
2022-10-24x86: fix VENDOR_MAX enum valueMartin Liska1-1/+3
2022-10-24RISC-V: Support --target-help for -mcpu/-mtuneKito Cheng1-0/+46
2022-10-21Enable AMD znver4 support and add instruction reservationsTejas Joshi3-28/+24
2022-10-21Support Intel AVX-VNNI-INT8Kong Lingling4-1/+26
2022-10-21Support Intel AVX-IFMAHongyu Wang4-1/+23
2022-10-17Enable REE for H8Jeff Law1-0/+2
2022-10-17Initial Meteorlake SupportHu, Lin12-0/+6
2022-10-17Initial Raptorlake SupportHaochen Jiang2-0/+4
2022-10-10arc: Remove obsolete mRcq and mRcw options.Claudiu Zissulescu1-2/+0
2022-09-29aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford1-0/+12
2022-09-29aarch64: Tweak contents of flags_on/off fieldsRichard Sandiford1-8/+6
2022-09-29aarch64: Make more use of aarch64_feature_flagsRichard Sandiford1-9/+10
2022-09-29aarch64: Tweak constness of option-related dataRichard Sandiford1-13/+13
2022-09-29aarch64: Avoid std::string in static dataRichard Sandiford1-2/+2
2022-09-29aarch64: Simplify generation of .arch stringsRichard Sandiford1-196/+47
2022-09-29aarch64: Simplify feature definitionsRichard Sandiford1-11/+18
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