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2022-02-09i386: -mno-xsave should disable all relevant ISA flags [PR104462]Uros Bizjak1-1/+2
2022-01-24properly disable -fsplit-stack on non-glibc targets [PR104170]Jakub Jelinek2-4/+6
2022-01-24RISC-V: Do not emit zcisr and zifencei if i-ext is 2.0Kito Cheng1-2/+12
2022-01-21x86: Properly disable -fsplit-stack support on non-glibc targetsH.J. Lu1-6/+11
2022-01-21Disable -fsplit-stack support on non-glibc targetsSören Tempel1-4/+10
2022-01-18RISC-V: Fix use-after-free error in `parse_multiletter_ext'Maciej W. Rozycki1-1/+1
2022-01-18riscv: fix -Wformat-diag errors.Martin Liska1-8/+8
2022-01-17Change references of .c files to .cc filesMartin Liska4-5/+5
2022-01-17Rename .c files to .cc files.Martin Liska50-0/+0
2022-01-14ARM: fix -Wformat= errorMartin Liska1-1/+1
2022-01-13Fix -Wformat-diag for ARM target.Martin Liska1-6/+6
2022-01-07RISC-V: Minimal support of vector extensionsKito Cheng1-0/+86
2022-01-07RISC-V: Allow extension name contain digitKito Cheng1-4/+38
2022-01-04x86: Update model value for Alderlake and RocketlakeCui,Lili1-0/+2
2022-01-03Update copyright years.Jakub Jelinek57-57/+57
2021-12-04RISC-V: Add implied defines of Zk, Zkn and ZksSiYu Wu1-1/+15
2021-12-04RISC-V: Add option defines for Scalar CryptographySiYu Wu1-0/+22
2021-11-11RISC-V: Fix wrong zifencei handling in riscv_subset_list::to_stringKito Cheng1-1/+1
2021-11-10[PR/target 102957] Allow Z*-ext extension with only 2 char.Kito Cheng1-1/+0
2021-10-25RISC-V: Minimal support of bitmanip extensionKito Cheng1-0/+10
2021-10-05Mark argument as unusedJan-Benedict Glaw1-1/+2
2021-09-21arm: pass architecture extensions to assembler if supportedRichard Earnshaw1-0/+10
2021-09-17x86: Update -mtune=tremontH.J. Lu1-1/+1
2021-09-13i386: support micro-levels in target{,_clone} attrs [PR101696]Martin Liska3-0/+61
2021-09-08AVX512FP16: Initial support for AVX512FP16 feature and scalar _Float16 instru...Guo, Xuepeng4-2/+28
2021-08-12arc: Small data doesn't need fcommon optionClaudiu Zissulescu1-3/+1
2021-07-18x86: Enable the GPR only instructions for -mgeneral-regs-onlyH.J. Lu1-2/+25
2021-06-30[amdgcn] Use frame pointer for CFA expressions.Hafiz Abid Qadeer1-1/+1
2021-06-18arm: Fix multilib mapping for CDE extensions [PR100856].Srinath Parvathaneni1-6/+41
2021-06-07Reformat target.def for better parsing.Martin Liska1-16/+16
2021-06-03arc: Remove obsolete optionsClaudiu Zissulescu1-1/+0
2021-05-19RISC-V: Properly parse the letter 'p' in '-march'.Geng Qi1-33/+35
2021-05-18Use startswith in targets.Martin Liska3-4/+4
2021-05-10arc: Fix compilation warnings.Claudiu Zissulescu1-1/+1
2021-04-27Synchronize Rocket Lake's processor_names and processor_cost_table with proce...Cui,Lili1-1/+1
2021-04-21x86: Add -mmwait for -mgeneral-regs-onlyH.J. Lu1-0/+15
2021-04-12Add rocketlake to gcc.Cui,Lili3-2/+13
2021-04-12Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2Cui,Lili1-0/+1
2021-03-24i386: fix -march=amd crashMartin Liska1-1/+1
2021-03-23RISC-V: Add riscv{32,64}be with big endian as defaultMarcus Comstedt1-0/+5
2021-03-09arm: fix bootstrap failure following automatic mode selection patchRichard Earnshaw1-1/+1
2021-03-03arm: Ignore --with-mode when CPU only supports one instruction set.Richard Earnshaw1-6/+43
2021-03-02IBM Z: arch14: Add command line optionsAndreas Krebbel1-0/+4
2021-01-28RISC-V: Fix -march option parsing when extension exists.Xing GUO1-3/+1
2021-01-14i386: Resolve variable shadowing in i386-options.c [PR98671]Uros Bizjak1-1/+1
2021-01-08RISC-V: Implement new style of architecture extension test macros.Kito Cheng1-0/+5
2021-01-08RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.hKito Cheng1-66/+1
2021-01-04Update copyright years.Jakub Jelinek57-57/+57
2020-12-11Fix feature check for HRESET/AVX_VNNI/UINTRHongyu1-10/+15
2020-12-05X86_64: Enable support for next generation AMD Zen3 CPU.Venkataramanan Kumar3-1/+34
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