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2023-08-29analyzer: improve strdup handling [PR105899]David Malcolm3-9/+48
gcc/analyzer/ChangeLog: PR analyzer/105899 * kf.cc (kf_strdup::impl_call_pre): Set size of dynamically-allocated buffer. Simulate copying the string from the source region to the new buffer. gcc/testsuite/ChangeLog: PR analyzer/105899 * c-c++-common/analyzer/pr99193-2.c: Add -Wno-analyzer-too-complex. * gcc.dg/analyzer/strdup-1.c: Include "analyzer-decls.h". (test_concrete_strlen): New. (test_symbolic_strlen): New. Signed-off-by: David Malcolm <dmalcolm@redhat.com>
2023-08-29RISC-V: Fix one ICE for vect test vect-multitypes-5Pan Li1-0/+23
There will be one ICE when build vect-multitypes-5.c similar as below: riscv64-unknown-elf-gcc -O3 \ -march=rv64imafdcv -mabi=lp64d -mcmodel=medlow \ -fdiagnostics-plain-output -flto -ffat-lto-objects \ --param riscv-autovec-preference=scalable -Wno-psabi \ -ftree-vectorize -fno-tree-loop-distribute-patterns \ -fno-vect-cost-model -fno-common -O2 -fdump-tree-vect-details \ gcc/testsuite/gcc.dg/vect/vect-multitypes-5.c -o test.elf -lm The below RTL is not well handled in riscv_legitimize_const_move, and then fall through to the default pass. Then the default force_const_mem will NULL_RTX, and will have ICE when operating one the NULL_RTX. (const:DI (plus:DI (symbol_ref:DI ("ic") [flags 0x2] <var_decl 0x7fe57740be10 ic>) (const_poly_int:DI [16, 16]))) This patch would like to take care of this rtl in riscv_legitimize_const_move. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored-By: Ju-Zhe Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/riscv.cc (riscv_legitimize_poly_move): New declaration. (riscv_legitimize_const_move): Handle ref plus const poly.
2023-08-29RISC-V: Add stub support for existing extensions (unprivileged)Tsukasa OI2-0/+32
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported standard unprivileged extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c except not yet merged 'Zce', 'Zcmp' and 'Zcmt' support). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from unprivileged extensions. (riscv_ext_version_table): Add stub support for all unprivileged extensions supported by Binutils as well as 'Zce', 'Zcmp', 'Zcmt'. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-31.c: New test for a stub unprivileged extension 'Zcb' with some implications.
2023-08-29RISC-V: Add stub support for existing extensions (vendor)Tsukasa OI2-0/+29
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. This commit adds stub supported vendor extensions to riscv_ext_version_table (no riscv_implied_info entries to add; all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Add stub support for all vendor extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-30.c: New test for a stub vendor extension 'XVentanaCondOps'.
2023-08-29RISC-V: Add stub support for existing extensions (privileged)Tsukasa OI2-0/+53
After commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions, we have no guarantee that we can share the same architectural string with Binutils (specifically, the assembler). To avoid compilation errors on shared Assembler-C/C++ projects or programs with inline assembler, GCC should support almost all extensions that Binutils support, even if the GCC itself does not touch a thing. As a start, this commit adds stub supported *privileged* extensions to riscv_ext_version_table and its implications to riscv_implied_info (all information is copied from Binutils' bfd/elfxx-riscv.c). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_implied_info): Add implications from privileged extensions. (riscv_ext_version_table): Add stub support for all privileged extensions supported by Binutils. gcc/testsuite/ChangeLog: * gcc.target/riscv/predef-29.c: New test for a stub privileged extension 'Smstateen' with some implications.
2023-08-29RISC-V: Make PR 102957 tests more comprehensiveTsukasa OI1-0/+5
Commit c283c4774d1c ("RISC-V: Throw compilation error for unknown extensions") changed how do we handle unknown extensions and commit 6f709f79c915a ("[committed] [RISC-V] Fix expected diagnostic messages in testsuite") "fixed" test failures caused by that change (on pr102957.c, by testing the error message after the first change). However, the latter change will partially break the original intent of PR 102957 test case because we wanted to make sure that we can parse a valid two-letter extension name. Fortunately, there is a valid two-letter extension name, 'Zk' (standard scalar cryptography extension superset with NIST algorithm suite). This commit adds pr102957-2.c to make sure that there will be no errors if we parse a valid two-letter extension name. gcc/testsuite/ChangeLog: * gcc.target/riscv/pr102957-2.c: New test case using the 'Zk' extension to continue testing whether we can use valid two-letter extensions.
2023-08-29RISC-V: Refactor and clean expand_cond_len_{unop,binop,ternop}Lehua Ding3-126/+58
This patch refactors the codes of expand_cond_len_{unop,binop,ternop}. Introduces a new unified function expand_cond_len_op to do the main thing. The expand_cond_len_{unop,binop,ternop} functions only care about how to pass the operands to the intrinsic patterns. gcc/ChangeLog: * config/riscv/autovec.md: Adjust * config/riscv/riscv-protos.h (RVV_VUNDEF): Clean. (get_vlmax_rtx): Exported. * config/riscv/riscv-v.cc (emit_nonvlmax_fp_ternary_tu_insn): Deleted. (emit_vlmax_masked_gather_mu_insn): Adjust. (get_vlmax_rtx): New func. (expand_load_store): Adjust. (expand_cond_len_unop): Call expand_cond_len_op. (expand_cond_len_op): New subroutine. (expand_cond_len_binop): Call expand_cond_len_op. (expand_cond_len_ternop): Call expand_cond_len_op. (expand_lanes_load_store): Adjust.
2023-08-29MAINTAINERS: Add myself to write after approvalTsukasa OI1-0/+1
ChangeLog: * MAINTAINERS: Add myself.
2023-08-29tree-ssa-math-opts: Improve uaddc/usubc pattern matching [PR111209]Jakub Jelinek2-1/+196
The uaddc/usubc usual matching is of the .{ADD,SUB}_OVERFLOW pair in the middle, which adds/subtracts carry-in (from lower limbs) and computes carry-out (to higher limbs). Before optimizations (unless user writes it intentionally that way already), all the steps look the same, but optimizations simplify the handling of the least significant limb (one which adds/subtracts 0 carry-in) to just a single .{ADD,SUB}_OVERFLOW and the handling of the most significant limb if the computed carry-out is ignored to normal addition/subtraction of multiple operands. Now, match_uaddc_usubc has code to turn that least significant .{ADD,SUB}_OVERFLOW call into .U{ADD,SUB}C call with 0 carry-in if a more significant limb above it is matched into .U{ADD,SUB}C; this isn't necessary for functionality, as .ADD_OVERFLOW (x, y) is functionally equal to .UADDC (x, y, 0) (provided the types of operands are the same and result is complex type with that type element), and it also has code to match the most significant limb with ignored carry-out (in that case one pattern match turns both the penultimate limb pair of .{ADD,SUB}_OVERFLOW into .U{ADD,SUB}C and the addition/subtraction of the 4 values (2 carries) into another .U{ADD,SUB}C. As the following patch shows, what we weren't handling is the case when one uses either the __builtin_{add,sub}c builtins or hand written forms thereof (either __builtin_*_overflow or even that written by hand) for just 2 limbs, where the least significant has 0 carry-in and the most significant ignores carry-out. The following patch matches that, e.g. _16 = .ADD_OVERFLOW (_1, _2); _17 = REALPART_EXPR <_16>; _18 = IMAGPART_EXPR <_16>; _15 = _3 + _4; _12 = _15 + _18; into _16 = .UADDC (_1, _2, 0); _17 = REALPART_EXPR <_16>; _18 = IMAGPART_EXPR <_16>; _19 = .UADDC (_3, _4, _18); _12 = IMAGPART_EXPR <_19>; so that we can emit better code. As the 2 later comments show, we must do that carefully, because the pass walks the IL from first to last stmt in a bb and we must avoid pattern matching this way something that should be matched on a later instruction differently. 2023-08-29 Jakub Jelinek <jakub@redhat.com> PR middle-end/79173 PR middle-end/111209 * tree-ssa-math-opts.cc (match_uaddc_usubc): Match also just 2 limb uaddc/usubc with 0 carry-in on lower limb and ignored carry-out on higher limb. Don't match it though if it could be matched later on 4 argument addition/subtraction. * gcc.target/i386/pr79173-12.c: New test.
2023-08-29MATCH: Move `(x | y) & (~x ^ y)` over to use bitwise_inverted_equal_pAndrew Pinski2-2/+52
This moves the match pattern `(x | y) & (~x ^ y)` over to use bitwise_inverted_equal_p. This now also allows to optmize comparisons and also catches the missed `(~x | y) & (x ^ y)` transformation into `~x & y`. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: PR tree-optimization/111147 * match.pd (`(x | y) & (~x ^ y)`) Use bitwise_inverted_equal_p instead of matching bit_not. gcc/testsuite/ChangeLog: PR tree-optimization/111147 * gcc.dg/tree-ssa/cmpbit-4.c: New test.
2023-08-29vect test: Remove xfail for riscvJuzhe-Zhong1-1/+1
We are planning to enable "vect" testsuite with scalable vector auto-vectorization. This case XPASS: XPASS: gcc.dg/vect/no-scevccp-outer-12.c scan-tree-dump-times vect "OUTER LOOP VECTORIZED." 1 like ARM SVE. gcc/testsuite/ChangeLog: * gcc.dg/vect/no-scevccp-outer-12.c: Add riscv xfail.
2023-08-29arm: Fix bootstrap / add missing initializer in MVE type_suffixesChristophe Lyon1-1/+1
My recent patch r14-3519-g9bae37ec8dc320 (arm: [MVE intrinsics] add support for p8 and p16 polynomial types) added a new member to type_suffix_info, but I forgot to add the corresponding initializer to type_suffixes. Committed as obvious. 2023-08-29 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins.cc (type_suffixes): Add missing initializer.
2023-08-29RISC-V: Fix ASM check of vlmax_switch_vtype-16.cJuzhe-Zhong1-1/+1
Notice there is a failure: FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c -O2 scan-assembler-times vsetvli\\s+zero,\\s*zero 2 Fix "2" into "3", the assembly is correct and better. Committed. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Fix ASM check.
2023-08-29RISC-V: Fix AVL/VL get ICE[VSETVL PASS]Juzhe-Zhong2-16/+31
Fix bunch of ICE in "vect" testsuite: FAIL: gcc.dg/vect/vect-alias-check-16.c (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-16.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-16.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-20.c (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-20.c (test for excess errors) FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (internal compiler error: Segmentation fault) FAIL: gcc.dg/vect/vect-alias-check-20.c -flto -ffat-lto-objects (test for excess errors) gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_insn_info::get_avl_or_vl_reg): New function. (pass_vsetvl::compute_local_properties): Fix bug. (pass_vsetvl::commit_vsetvls): Ditto. * config/riscv/riscv-vsetvl.h: New function.
2023-08-29RISC-V: Fix error combine of pred_mov patternLehua Ding5-49/+106
This patch fix PR110943 which will produce some error code. This is because the error combine of some pred_mov pattern. Consider this code: ``` void foo9 (void *base, void *out, size_t vl) { int64_t scalar = *(int64_t*)(base + 100); vint64m2_t v = __riscv_vmv_v_x_i64m2 (0, 1); *(vint64m2_t*)out = v; } ``` RTL before combine pass: ``` (insn 11 10 12 2 (set (reg/v:RVVM2DI 134 [ v ]) (if_then_else:RVVM2DI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (const_int 1 [0x1]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (const_vector:RVVM2DI repeat [ (const_int 0 [0]) ]) (unspec:RVVM2DI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) "/app/example.c":6:20 1089 {pred_movrvvm2di}) (insn 14 13 0 2 (set (mem:RVVM2DI (reg/v/f:DI 136 [ out ]) [1 MEM[(vint64m2_t *)out_4(D)]+0 S[32, 32] A128]) (reg/v:RVVM2DI 134 [ v ])) "/app/example.c":7:23 717 {*movrvvm2di_whole}) ``` RTL after combine pass: ``` (insn 14 13 0 2 (set (mem:RVVM2DI (reg:DI 138) [1 MEM[(vint64m2_t *)out_4(D)]+0 S[32, 32] A128]) (if_then_else:RVVM2DI (unspec:RVVMF32BI [ (const_vector:RVVMF32BI repeat [ (const_int 1 [0x1]) ]) (const_int 1 [0x1]) (const_int 2 [0x2]) repeated x2 (const_int 0 [0]) (reg:SI 66 vl) (reg:SI 67 vtype) ] UNSPEC_VPREDICATE) (const_vector:RVVM2DI repeat [ (const_int 0 [0]) ]) (unspec:RVVM2DI [ (reg:SI 0 zero) ] UNSPEC_VUNDEF))) "/app/example.c":7:23 1089 {pred_movrvvm2di}) ``` This combine change the semantics of insn 14. I split @pred_mov pattern and restrict the conditon of @pred_mov. PR target/110943 gcc/ChangeLog: * config/riscv/predicates.md (vector_const_int_or_double_0_operand): New predicate. * config/riscv/riscv-vector-builtins.cc (function_expander::function_expander): force_reg mem target operand. * config/riscv/vector.md (@pred_mov<mode>): Wrapper. (*pred_mov<mode>): Remove imm -> reg pattern. (*pred_broadcast<mode>_imm): Add imm -> reg pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Adjust. * gcc.target/riscv/rvv/base/pr110943.c: New test.
2023-08-29mklog: fix bugs of --append optionLehua Ding1-3/+5
This little patch fix two bugs of mklog.py with --append option. The first bug is that the regexp used is not accurate enough to determine the top of diff area. The second bug is that if `---` is not a true start, it needs to be added back to the patch file. And with additional fix Python code format error, which Martin reported. contrib/ChangeLog: * mklog.py: Fix bugs.
2023-08-29LoongArch: Enable '-free' starting at -O2.Lulu Cheng3-2/+28
gcc/ChangeLog: * common/config/loongarch/loongarch-common.cc: Enable '-free' on O2 and above. * doc/invoke.texi: Modify the description information of the '-free' compilation option and add the LoongArch description. gcc/testsuite/ChangeLog: * gcc.target/loongarch/sign-extend.c: New test.
2023-08-29Daily bump.GCC Administrator3-1/+407
2023-08-28RISC-V: Fix documentation of __builtin_riscv_pauseTsukasa OI1-3/+3
This built-in does not imply the 'Xgnuzihintpausestate' extension. It does not change architectural state (because all HINTs are prohibited from doing that). gcc/ChangeLog: * doc/extend.texi: Fix the description of __builtin_riscv_pause.
2023-08-28RISC-V: __builtin_riscv_pause for all environmentTsukasa OI8-13/+41
The "pause" RISC-V hint instruction requires the 'Zihintpause' extension (in the assembler). However, GCC emits "pause" unconditionally, making an assembler error while compiling code with __builtin_riscv_pause while the 'Zihintpause' extension disabled. However, the "pause" instruction code (0x0100000f) is a HINT and emitting its instruction code is safe in any environment. This commit implements handling for the 'Zihintpause' extension and emits ".insn 0x0100000f" instead of "pause" only if the extension is disabled (making the diagnostics better). gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_ext_version_table): Implement the 'Zihintpause' extension, version 2.0. (riscv_ext_flag_table) Add 'Zihintpause' handling. * config/riscv/riscv-builtins.cc: Remove availability predicate "always" and add "hint_pause". (riscv_builtins) : Add "pause" extension. * config/riscv/riscv-opts.h (MASK_ZIHINTPAUSE, TARGET_ZIHINTPAUSE): New. * config/riscv/riscv.md (riscv_pause): Adjust output based on TARGET_ZIHINTPAUSE. gcc/testsuite/ChangeLog: * gcc.target/riscv/builtin_pause.c: Removed. * gcc.target/riscv/zihintpause-1.c: New test when the 'Zihintpause' extension is enabled. * gcc.target/riscv/zihintpause-2.c: Likewise. * gcc.target/riscv/zihintpause-noarch.c: New test when the 'Zihintpause' extension is disabled.
2023-08-28Fix cond-bool-2.c on powerpc and other targetsAndrew Pinski1-1/+1
This adds `--param logical-op-non-short-circuit=1` to the tescase so it becomes a target indepdendent testcase now. I filed PR 111217 as the variant of the testcase which fails indepdendently of the param. Committed as obvious after testing to make sure it passes on powerpc now. gcc/testsuite/ChangeLog: PR testsuite/111215 * gcc.dg/tree-ssa/cond-bool-2.c: Add `--param logical-op-non-short-circuit=1` to the options.
2023-08-28MATCH: Move `(X & ~Y) | (~X & Y)` over to use bitwise_inverted_equal_pAndrew Pinski3-7/+41
This moves the pattern `(X & ~Y) | (~X & Y)` to use bitwise_inverted_equal_p so we can simplify earlier the case where X and Y are defined by comparisons. We were able to optimize to (!X)^(!Y) in the end due to the pattern added in r14-3110-g7fb65f102851248bafa0815 and the older pattern r13-4620-g4d9db4bdd458 . But folding it earlier is better. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. Note pr87009.c now gets `return x ^ s; in one case where the test had been expecting `return s ^ x;` both are valid and would be expectly the same; just we now chose a slightly different order of simplification which causes the order of the operands to be different. gcc/ChangeLog: * match.pd (`(X & ~Y) | (~X & Y)`): Use bitwise_inverted_equal_p instead of specifically checking for ~X. gcc/testsuite/ChangeLog: * gcc.dg/tree-ssa/cmpbit-3.c: New test. * gcc.dg/pr87009.c: Update test.
2023-08-28MATCH: Remove redundant pattern for `(x | y) & ~x`Andrew Pinski1-8/+0
After r14-2885-gb9237226fdc938, this pattern becomes redundant as we match it using bitwise_inverted_equal_p. There is already a testcase (gcc.dg/nand.c) for this pattern and it still passes after the removal. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: PR tree-optimization/111146 * match.pd (`(x | y) & ~x`, `(x & y) | ~x`): Remove redundant pattern.
2023-08-28PHIOPT: Add dump for match and simplify and early phioptAndrew Pinski1-26/+44
This adds dump on the full result of the match-and-simplify for phiopt and specifically to know if we are rejecting something due to being in early phi-opt. OK? Bootstrapped and tested on x86_64-linux-gnu with no regressions. gcc/ChangeLog: * tree-ssa-phiopt.cc (gimple_simplify_phiopt): Add dump information when resimplify returns true. (match_simplify_replacement): Print only if accepted the match-and-simplify result rather than the full sequence.
2023-08-28RISC-V: Fix uninitialized probability for GIMPLE IR testsJuzhe-Zhong1-1/+12
This patch fix unitialized probability in GIMPLE IR code tests: FAIL: gcc.dg/vect/slp-reduc-10a.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10a.c (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10a.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10a.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10b.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10b.c (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10b.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10b.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10c.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10c.c (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10c.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10c.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10d.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10d.c (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10d.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10d.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10e.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10e.c (test for excess errors) FAIL: gcc.dg/vect/slp-reduc-10e.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/slp-reduc-10e.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-cond-arith-2.c (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/vect-cond-arith-2.c (test for excess errors) FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects (internal compiler error: in compute_probabilities, at config/riscv/riscv-vsetvl.cc:4358) FAIL: gcc.dg/vect/vect-cond-arith-2.c -flto -ffat-lto-objects (test for excess errors) gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion): Skip never probability. (pass_vsetvl::compute_probabilities): Fix unitialized probability.
2023-08-28RISC-V: Disable user vsetvl fusion into EMPTY or DIRTY (Polluted EMPTY) blockJuzhe-Zhong1-2/+36
This patch is fixing these bunch of ICE in "vect" testsuite: FAIL: gcc.dg/vect/no-scevccp-outer-2.c (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/no-scevccp-outer-2.c (test for excess errors) FAIL: gcc.dg/vect/pr109025.c (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/pr109025.c (test for excess errors) FAIL: gcc.dg/vect/pr109025.c -flto -ffat-lto-objects (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/pr109025.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/pr42604.c (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/pr42604.c (test for excess errors) FAIL: gcc.dg/vect/pr42604.c -flto -ffat-lto-objects (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/pr42604.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-double-reduc-3.c (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/vect-double-reduc-3.c (test for excess errors) FAIL: gcc.dg/vect/vect-double-reduc-3.c -flto -ffat-lto-objects (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/vect-double-reduc-3.c -flto -ffat-lto-objects (test for excess errors) FAIL: gcc.dg/vect/vect-double-reduc-7.c (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/vect-double-reduc-7.c (test for excess errors) FAIL: gcc.dg/vect/vect-double-reduc-7.c -flto -ffat-lto-objects (internal compiler error: in anticipatable_occurrence_p, at config/riscv/riscv-vsetvl.cc:314) FAIL: gcc.dg/vect/vect-double-reduc-7.c -flto -ffat-lto-objects (test for excess errors) gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::earliest_fusion): Fix bug.
2023-08-28arm: [MVE intrinsics] rework vmullbq_poly vmulltq_polyChristophe Lyon4-248/+6
Implement vmull[bt]q_poly using the new MVE builtins framework. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-base.cc (vmullbq_poly) (vmulltq_poly): New. * config/arm/arm-mve-builtins-base.def (vmullbq_poly) (vmulltq_poly): New. * config/arm/arm-mve-builtins-base.h (vmullbq_poly) (vmulltq_poly): New. * config/arm/arm_mve.h (vmulltq_poly): Remove. (vmullbq_poly): Remove. (vmullbq_poly_m): Remove. (vmulltq_poly_m): Remove. (vmullbq_poly_x): Remove. (vmulltq_poly_x): Remove. (vmulltq_poly_p8): Remove. (vmullbq_poly_p8): Remove. (vmulltq_poly_p16): Remove. (vmullbq_poly_p16): Remove. (vmullbq_poly_m_p8): Remove. (vmullbq_poly_m_p16): Remove. (vmulltq_poly_m_p8): Remove. (vmulltq_poly_m_p16): Remove. (vmullbq_poly_x_p8): Remove. (vmullbq_poly_x_p16): Remove. (vmulltq_poly_x_p8): Remove. (vmulltq_poly_x_p16): Remove. (__arm_vmulltq_poly_p8): Remove. (__arm_vmullbq_poly_p8): Remove. (__arm_vmulltq_poly_p16): Remove. (__arm_vmullbq_poly_p16): Remove. (__arm_vmullbq_poly_m_p8): Remove. (__arm_vmullbq_poly_m_p16): Remove. (__arm_vmulltq_poly_m_p8): Remove. (__arm_vmulltq_poly_m_p16): Remove. (__arm_vmullbq_poly_x_p8): Remove. (__arm_vmullbq_poly_x_p16): Remove. (__arm_vmulltq_poly_x_p8): Remove. (__arm_vmulltq_poly_x_p16): Remove. (__arm_vmulltq_poly): Remove. (__arm_vmullbq_poly): Remove. (__arm_vmullbq_poly_m): Remove. (__arm_vmulltq_poly_m): Remove. (__arm_vmullbq_poly_x): Remove. (__arm_vmulltq_poly_x): Remove.
2023-08-28arm: [MVE intrinsics] add unspec_mve_function_exact_insn_vmull_polyChristophe Lyon1-1/+55
Introduce a function that will be used to build vmull[bt]q_poly intrinsics that use poly types. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-functions.h (class unspec_mve_function_exact_insn_vmull_poly): New.
2023-08-28arm: [MVE intrinsics] add binary_widen_poly shapeChristophe Lyon2-0/+50
This patch adds the binary_widen_poly shape description. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_widen_poly): New. * config/arm/arm-mve-builtins-shapes.h (binary_widen_poly): New.
2023-08-28arm: [MVE intrinsics] add support for U and p formats in parse_element_typeChristophe Lyon1-0/+16
Introduce these two format specifiers to define the shape of vmull[bt]q_poly intrinsics. 'U' is used to define a double-width unsigned 'p' is used to define an element of 'poly' type. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (parse_element_type): Add support for 'U' and 'p' format specifiers.
2023-08-28arm: [MVE intrinsics] add support for p8 and p16 polynomial typesChristophe Lyon3-1/+12
Although they look like aliases for u8 and u16, we need to define them so that we can handle p8 and p16 suffixes with the general framework. They will be used by vmull[bt]q_poly intrinsics. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins.cc (type_suffixes): Handle poly_p field.. (TYPES_poly_8_16): New. (poly_8_16): New. * config/arm/arm-mve-builtins.def (p8): New type suffix. (p16): Likewise. * config/arm/arm-mve-builtins.h (enum type_class_index): Add TYPE_poly. (struct type_suffix_info): Add poly_p field.
2023-08-28arm: [MVE intrinsics] rework vmullbq_int vmulltq_intChristophe Lyon4-648/+6
Implement vmullbq_int, vmulltq_int using the new MVE builtins framework. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-base.cc (vmullbq_int, vmulltq_int): New. * config/arm/arm-mve-builtins-base.def (vmullbq_int, vmulltq_int): New. * config/arm/arm-mve-builtins-base.h (vmullbq_int, vmulltq_int): New. * config/arm/arm_mve.h (vmulltq_int): Remove. (vmullbq_int): Remove. (vmullbq_int_m): Remove. (vmulltq_int_m): Remove. (vmullbq_int_x): Remove. (vmulltq_int_x): Remove. (vmulltq_int_u8): Remove. (vmullbq_int_u8): Remove. (vmulltq_int_s8): Remove. (vmullbq_int_s8): Remove. (vmulltq_int_u16): Remove. (vmullbq_int_u16): Remove. (vmulltq_int_s16): Remove. (vmullbq_int_s16): Remove. (vmulltq_int_u32): Remove. (vmullbq_int_u32): Remove. (vmulltq_int_s32): Remove. (vmullbq_int_s32): Remove. (vmullbq_int_m_s8): Remove. (vmullbq_int_m_s32): Remove. (vmullbq_int_m_s16): Remove. (vmullbq_int_m_u8): Remove. (vmullbq_int_m_u32): Remove. (vmullbq_int_m_u16): Remove. (vmulltq_int_m_s8): Remove. (vmulltq_int_m_s32): Remove. (vmulltq_int_m_s16): Remove. (vmulltq_int_m_u8): Remove. (vmulltq_int_m_u32): Remove. (vmulltq_int_m_u16): Remove. (vmullbq_int_x_s8): Remove. (vmullbq_int_x_s16): Remove. (vmullbq_int_x_s32): Remove. (vmullbq_int_x_u8): Remove. (vmullbq_int_x_u16): Remove. (vmullbq_int_x_u32): Remove. (vmulltq_int_x_s8): Remove. (vmulltq_int_x_s16): Remove. (vmulltq_int_x_s32): Remove. (vmulltq_int_x_u8): Remove. (vmulltq_int_x_u16): Remove. (vmulltq_int_x_u32): Remove. (__arm_vmulltq_int_u8): Remove. (__arm_vmullbq_int_u8): Remove. (__arm_vmulltq_int_s8): Remove. (__arm_vmullbq_int_s8): Remove. (__arm_vmulltq_int_u16): Remove. (__arm_vmullbq_int_u16): Remove. (__arm_vmulltq_int_s16): Remove. (__arm_vmullbq_int_s16): Remove. (__arm_vmulltq_int_u32): Remove. (__arm_vmullbq_int_u32): Remove. (__arm_vmulltq_int_s32): Remove. (__arm_vmullbq_int_s32): Remove. (__arm_vmullbq_int_m_s8): Remove. (__arm_vmullbq_int_m_s32): Remove. (__arm_vmullbq_int_m_s16): Remove. (__arm_vmullbq_int_m_u8): Remove. (__arm_vmullbq_int_m_u32): Remove. (__arm_vmullbq_int_m_u16): Remove. (__arm_vmulltq_int_m_s8): Remove. (__arm_vmulltq_int_m_s32): Remove. (__arm_vmulltq_int_m_s16): Remove. (__arm_vmulltq_int_m_u8): Remove. (__arm_vmulltq_int_m_u32): Remove. (__arm_vmulltq_int_m_u16): Remove. (__arm_vmullbq_int_x_s8): Remove. (__arm_vmullbq_int_x_s16): Remove. (__arm_vmullbq_int_x_s32): Remove. (__arm_vmullbq_int_x_u8): Remove. (__arm_vmullbq_int_x_u16): Remove. (__arm_vmullbq_int_x_u32): Remove. (__arm_vmulltq_int_x_s8): Remove. (__arm_vmulltq_int_x_s16): Remove. (__arm_vmulltq_int_x_s32): Remove. (__arm_vmulltq_int_x_u8): Remove. (__arm_vmulltq_int_x_u16): Remove. (__arm_vmulltq_int_x_u32): Remove. (__arm_vmulltq_int): Remove. (__arm_vmullbq_int): Remove. (__arm_vmullbq_int_m): Remove. (__arm_vmulltq_int_m): Remove. (__arm_vmullbq_int_x): Remove. (__arm_vmulltq_int_x): Remove.
2023-08-28arm: [MVE intrinsics] add binary_widen shapeChristophe Lyon2-2/+45
This patch adds the binary_widen shape description. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/: * config/arm/arm-mve-builtins-shapes.cc (binary_widen): New. * config/arm/arm-mve-builtins-shapes.h (binary_widen): New.
2023-08-28arm: [MVE intrinsics] add unspec_mve_function_exact_insn_vmullChristophe Lyon1-0/+74
Introduce a function that will be used to build vmull intrinsics with the _int variant. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-functions.h (class unspec_mve_function_exact_insn_vmull): New.
2023-08-28arm: [MVE intrinsics] factorize vmullbq vmulltqChristophe Lyon2-85/+38
Factorize vmullbq, vmulltq so that they use the same parameterized names. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/iterators.md (mve_insn): Add vmullb, vmullt. (isu): Add VMULLBQ_INT_S, VMULLBQ_INT_U, VMULLTQ_INT_S, VMULLTQ_INT_U. (supf): Add VMULLBQ_POLY_P, VMULLTQ_POLY_P, VMULLBQ_POLY_M_P, VMULLTQ_POLY_M_P. (VMULLBQ_INT, VMULLTQ_INT, VMULLBQ_INT_M, VMULLTQ_INT_M): Delete. (VMULLxQ_INT, VMULLxQ_POLY, VMULLxQ_INT_M, VMULLxQ_POLY_M): New. * config/arm/mve.md (mve_vmullbq_int_<supf><mode>) (mve_vmulltq_int_<supf><mode>): Merge into ... (@mve_<mve_insn>q_int_<supf><mode>) ... this. (mve_vmulltq_poly_p<mode>, mve_vmullbq_poly_p<mode>): Merge into ... (@mve_<mve_insn>q_poly_<supf><mode>): ... this. (mve_vmullbq_int_m_<supf><mode>, mve_vmulltq_int_m_<supf><mode>): Merge into ... (@mve_<mve_insn>q_int_m_<supf><mode>): ... this. (mve_vmullbq_poly_m_p<mode>, mve_vmulltq_poly_m_p<mode>): Merge into ... (@mve_<mve_insn>q_poly_m_<supf><mode>): ... this.
2023-08-28arm: [MVE intrinsics] Remove dead check for float type in parse_element_typeChristophe Lyon1-2/+1
Fix a likely copy/paste error, where we check if ch == 'f' after we checked it's either 's' or 'u'. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (parse_element_type): Remove dead check.
2023-08-28arm: [MVE intrinsics] fix binary_acca_int32 and binary_acca_int64 shapesChristophe Lyon1-2/+2
Fix these two shapes, where we were failing to check the last non-predicate parameter. 2023-08-14 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_acca_int32): Fix loop bound. (binary_acca_int64): Likewise.
2023-08-28[frange] Handle relations in LTGT_EXPR.Aldy Hernandez1-2/+17
LTGT_EXPR hasn't been handling relations, especially with NANs as a possibility. This handles them while documenting how relations work in a world with NANs. Basically we need to special case VREL_EQ before calling frelop_early_resolve. Note that VREL_EQ on entry to a range-op entry is really VREL_EQ U NAN, but to make sure about the NAN possibility, one must look at the operands. However, even VREL_EQ U NAN is false for LTGT_EXPR since the latter is just NE_EXPR without a NAN. After we handle VREL_EQ, we drop down to frelop_early_resolve pretending to be a NE_EXPR, and everything should just map correctly. 2023-08-28 Aldy Hernandez <aldyh@redhat.com> * range-op-float.cc (fold_range): Handle relations.
2023-08-28LoongArch: Remove redundant sign extension instructions caused by SLT ↵Lulu Cheng2-4/+63
instructions. Since the SLT instruction does not distinguish between 64-bit operations and 32-bit operations under the 64-bit LoongArch architecture, if the operand of slt is SImode, the sign extension of the operand needs to be displayed. But similar to the test case below, the sign extension is redundant: extern int src1, src2, src3; int test (void) { int data1 = src1 + src2; int data2 = src1 + src3; return data1 > data2 ? data1 : data2; } Assembly code before optimization: ... add.w $r4,$r4,$r14 add.w $r13,$r13,$r14 slli.w $r12,$r4,0 slli.w $r14,$r13,0 slt $r12,$r12,$r14 masknez $r4,$r4,$r12 maskeqz $r12,$r13,$r12 or $r4,$r4,$r12 slli.w $r4,$r4,0 ... After optimization: ... add.w $r12,$r12,$r14 add.w $r13,$r13,$r14 slt $r4,$r12,$r13 masknez $r12,$r12,$r4 maskeqz $r4,$r13,$r4 or $r4,$r12,$r4 ... Similar to this test example, the two operands of SLT are obtained by the addition operation, and add.w implicitly sign-extends, so the two operands of SLT do not require sign-extend. gcc/ChangeLog: * config/loongarch/loongarch.cc (loongarch_expand_conditional_move): Optimize the function implementation. gcc/testsuite/ChangeLog: * gcc.target/loongarch/slt-sign-extend.c: New test.
2023-08-28RISC-V: Fix VSETVL test failuresJuzhe-Zhong7-12/+4
Committed. Fix failures: FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 5 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 5 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vlm\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 5 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fno-use-linker-plugin -flto-partition=none scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9][0-9]\\:\\s+vle32\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 1 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle16\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 2 FAIL: gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects scan-assembler-times add\\ta[0-7],a[0-7],a[0-7]\\s+\\.L[0-9][0-9]\\:\\s+vle8\\.v\\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\\s*\\([a-x0-9]+\\) 3 gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vxrm-8.c: Adapt tests. * gcc.target/riscv/rvv/base/vxrm-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto.
2023-08-28Use vmaskmov{ps,pd} for VI48_128_256 when TARGET_AVX2 is not available.liuhongt1-18/+30
vpmaskmov{d,q} is available for TARGET_AVX2, vmaskmov{ps,ps} is available for TARGET_AVX, w/o TARGET_AVX2, we can use vmaskmov{ps,pd} for VI48_128_256 gcc/ChangeLog: PR target/111119 * config/i386/sse.md (V48_AVX2): Rename to .. (V48_128_256): .. this. (ssefltmodesuffix): Extend to V4SF/V8SF/V2DF/V4DF. (<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Change V48_AVX2 to V48_128_256, also generate vmaskmov{ps,pd} for integral modes when TARGET_AVX2 is not available. (<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto. (maskload<mode><sseintvecmodelower>): Change V48_AVX2 to V48_128_256. (maskstore<mode><sseintvecmodelower>): Ditto.
2023-08-28RISC-V: Refactor Phase 3 (Demand fusion) of VSETVL PASSJuzhe-Zhong58-1117/+765
This patch refactors the Phase 3 (Demand fusion) and rename it into Earliest fusion. I do the refactor for the following reasons: 1. Current implementation of phase 3 is doing too many things which makes the code quality quite messy and not easy to maintain. 2. The demand fusion I do previously is we explicitly make the fusion including how to fuse VSETVLs, where to make the VSETVL fusion happens, check the VSETVL fusion point (location) whether it is correct and optimal...etc. We are dong these things too much so I added these following functions: enum fusion_type get_backward_fusion_type (const bb_info *, const vector_insn_info &); bool hard_empty_block_p (const bb_info *, const vector_insn_info &) const; bool backward_demand_fusion (void); bool forward_demand_fusion (void); bool cleanup_illegal_dirty_blocks (void); to make sure the VSETV fusion is optimal and correct. I found in may downstream testing it is not the reliable and optimal approach. Instead, this patch is to use 'compute_earliest' which is the function of LCM to fuse multiple 'compatible' VSETVL demand info if they are having same earliest edge. We let LCM decide almost everything of demand fusion for us. The only thing we do (Not the LCM do) is just checking the VSETVLs demand info are compatible or not. That's all we need to do. I belive such approach is much more reliable and optimal than before (We have many testcases already to check this refactor patch). 3. Using LCM approach to do the demand fusion is more reliable and better CFG than before. ... Here is the basics of this patch approach: Consider this following case: for for for ... for if (...) VSETVL 1 demand: RATIO = 32 and TU policy. else if (...) VSETVL 2 demand: SEW = 16. else VSETVL 3 demand: MU policy. - 'compute_earliest' which output the earliest edge of VSETVL 1, VSETVL 2 and VSETVL 3. They are having same earliest edge which is outside the 1th inner-most loop. - Then, we check these 3 VSETVL demand info are compatible so fuse them into a single VSETVL info: demand SEW = 16, LMUL = MF2, TU, MU. - Then the later phase (phase 4) LCM PRE (partial reduandancy elimination) will hoist such VSETVL to the outer-most loop. So that we can get optimal codegen. gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vsetvl_vtype_change_only_p): New function. (after_or_same_p): Ditto. (find_reg_killed_by): Delete. (has_vsetvl_killed_avl_p): Ditto. (anticipatable_occurrence_p): Refactor. (any_set_in_bb_p): Delete. (count_regno_occurrences): Ditto. (backward_propagate_worthwhile_p): Ditto. (demands_can_be_fused_p): Ditto. (earliest_pred_can_be_fused_p): New function. (vsetvl_dominated_by_p): Ditto. (vector_insn_info::parse_insn): Refactor. (vector_insn_info::merge): Refactor. (vector_insn_info::dump): Refactor. (vector_infos_manager::vector_infos_manager): Refactor. (vector_infos_manager::all_empty_predecessor_p): Delete. (vector_infos_manager::all_same_avl_p): Ditto. (vector_infos_manager::create_bitmap_vectors): Refactor. (vector_infos_manager::free_bitmap_vectors): Refactor. (vector_infos_manager::dump): Refactor. (pass_vsetvl::update_block_info): New function. (enum fusion_type): Ditto. (pass_vsetvl::get_backward_fusion_type): Delete. (pass_vsetvl::hard_empty_block_p): Ditto. (pass_vsetvl::backward_demand_fusion): Ditto. (pass_vsetvl::forward_demand_fusion): Ditto. (pass_vsetvl::demand_fusion): Ditto. (pass_vsetvl::cleanup_illegal_dirty_blocks): Ditto. (pass_vsetvl::compute_local_properties): Ditto. (pass_vsetvl::earliest_fusion): New function. (pass_vsetvl::vsetvl_fusion): Ditto. (pass_vsetvl::commit_vsetvls): Refactor. (get_first_vsetvl_before_rvv_insns): Ditto. (pass_vsetvl::global_eliminate_vsetvl_insn): Ditto. (pass_vsetvl::cleanup_earliest_vsetvls): New function. (pass_vsetvl::df_post_optimization): Refactor. (pass_vsetvl::lazy_vsetvl): Ditto. * config/riscv/riscv-vsetvl.h: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Adapt test. * gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-15.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-27.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-28.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-29.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-35.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-36.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-46.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-48.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-66.c: * gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-69.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-72.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-76.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-77.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-82.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-83.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-84.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-89.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-93.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-94.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-95.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-96.c: Ditto. * gcc.target/riscv/rvv/vsetvl/ffload-5.c: Ditto. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto. * gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: Ditto. * gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-45.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-1.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-9.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-10.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-12.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-3.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-4.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-7.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-1.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-16.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: Ditto. * gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: Ditto. * gcc.target/riscv/rvv/vsetvl/avl_single-103.c: New test. * gcc.target/riscv/rvv/vsetvl/vlmax_conflict-13.c: New test.
2023-08-28Daily bump.GCC Administrator3-1/+254
2023-08-27RISC-V: Fix spill-11.c testsuite failureJeff Law1-2/+2
Jivan's work also results in using a different save/restore function for the spill-11 test. So the expected output needs minor adjusting gcc/testsuite * gcc.target/riscv/rvv/base/spill-11.c: Adjust expected output.
2023-08-27RISC-V: Fix spill-12 testJeff Law1-6/+1
Jivan's recent work on IRA results in more efficient code for this test. This adjusts the expected output for the removal of 5 instructions and conversion of an addi into a simple mv. gcc/testsuite * gcc.target/riscv/rvv/base/spill-12.c: Update expected output.
2023-08-27RISC-V: Fix xtheadcondmov-indirect.cJeff Law1-2/+2
The pressure sensitive scheduling change perturbs the output ever so slightly for this test. Seemed easiest to just turn that off rather than generalize the expected output enough to work across all the relevant optimization options. gcc/testsuite/ * gcc.target/riscv/xtheadcondmov-indirect.c: Turn off pressure sensitive scheduling.
2023-08-27analyzer: Move gcc.dg/analyzer tests to c-c++-common (1) [PR96395]benjamin priour120-619/+1136
First batch of moving tests from under gcc.dg/analyzer into c-c++-common/analyzer. C builtins are not recognized as such by C++, therefore this patch no longer uses tree.h:fndecl_built_in_p to recognize a builtin function, but rather the function names. Thus functions named as C builtins - such as calloc, sprintf ... - are recognized as such both in C and C++ sources by the analyzer. For user-declared functions named after builtins, the latters' function_decl tree are now preferred over the function_decl the user declared, even when the FE consider their declaration to mismatch (Wbuiltin-declaration-mismatch emitted). This mainly comes into account in the handling of these function attributes : the analyzer uses the builtin's attributes defined in gcc/builtins.def. Signed-off-by: benjamin priour <priour.be@gmail.com> gcc/analyzer/ChangeLog: PR analyzer/96395 * analyzer.h (class known_function): Add virtual casts to builtin_known_function. (class builtin_known_function): New subclass of known_function for builtins. * kf.cc (class kf_alloca): Now derived from builtin_known_function. (class kf_calloc): Likewise. (class kf_free): Likewise. (class kf_malloc): Likewise. (class kf_memcpy_memmove): Likewise. (class kf_memset): Likewise. (class kf_realloc): Likewise. (class kf_strchr): Likewise. (class kf_sprintf): Likewise. (class kf_strcat): Likewise. (class kf_strcpy): Likewise. (class kf_strdup): Likewise. (class kf_strlen): Likewise. (class kf_strndup): Likewise. (register_known_functions): Builtins are now registered as known_functions by name rather than by their BUILTIN_CODE. * known-function-manager.cc (get_normal_builtin): New overload. * known-function-manager.h: New overload declaration. * region-model.cc (region_model::get_builtin_kf): New function. * region-model.h (class region_model): Add declaration of get_builtin_kf. * sm-fd.cc: For called recognized as builtins, use the attributes of that builtin as defined in gcc/builtins.def rather than the user's. * sm-malloc.cc (malloc_state_machine::on_stmt): Likewise. gcc/testsuite/ChangeLog: PR analyzer/96395 * gcc.dg/analyzer/aliasing-3.c: Moved to... * c-c++-common/analyzer/aliasing-3.c: ...here. * gcc.dg/analyzer/aliasing-pr106473.c: Moved to... * c-c++-common/analyzer/aliasing-pr106473.c: ...here. * gcc.dg/analyzer/asm-x86-dyndbg-2.c: Moved to... * c-c++-common/analyzer/asm-x86-dyndbg-2.c: ...here. * gcc.dg/analyzer/asm-x86-lp64-2.c: Moved to... * c-c++-common/analyzer/asm-x86-lp64-2.c: ...here. * gcc.dg/analyzer/atomic-builtins-haproxy-proxy.c: Moved to... * c-c++-common/analyzer/atomic-builtins-haproxy-proxy.c: ...here. * gcc.dg/analyzer/atomic-builtins-qemu-sockets.c: Moved to... * c-c++-common/analyzer/atomic-builtins-qemu-sockets.c: ...here. * gcc.dg/analyzer/attr-malloc-6.c: Moved to... * c-c++-common/analyzer/attr-malloc-6.c: ...here. * gcc.dg/analyzer/attr-malloc-CVE-2019-19078-usb-leak.c: Moved to... * c-c++-common/analyzer/attr-malloc-CVE-2019-19078-usb-leak.c: ...here. * gcc.dg/analyzer/attr-tainted_args-1.c: Moved to... * c-c++-common/analyzer/attr-tainted_args-1.c: ...here. * gcc.dg/analyzer/call-summaries-pr107158.c: Moved to... * c-c++-common/analyzer/call-summaries-pr107158.c: ...here. * gcc.dg/analyzer/calloc-1.c: Moved to... * c-c++-common/analyzer/calloc-1.c: ...here. * gcc.dg/analyzer/compound-assignment-5.c: Moved to... * c-c++-common/analyzer/compound-assignment-5.c: ...here. * gcc.dg/analyzer/coreutils-cksum-pr108664.c: Moved to... * c-c++-common/analyzer/coreutils-cksum-pr108664.c: ...here. * gcc.dg/analyzer/coreutils-sum-pr108666.c: Moved to... * c-c++-common/analyzer/coreutils-sum-pr108666.c: ...here. * gcc.dg/analyzer/deref-before-check-pr108455-1.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr108455-1.c: ...here. * gcc.dg/analyzer/deref-before-check-pr108455-git-pack-revindex.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr108455-git-pack-revindex.c: ...here. * gcc.dg/analyzer/deref-before-check-pr108475-1.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr108475-1.c: ...here. * gcc.dg/analyzer/deref-before-check-pr108475-haproxy-tcpcheck.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr108475-haproxy-tcpcheck.c: ...here. * gcc.dg/analyzer/deref-before-check-pr109060-haproxy-cfgparse.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr109060-haproxy-cfgparse.c: ...here. * gcc.dg/analyzer/deref-before-check-pr109239-linux-bus.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr109239-linux-bus.c: ...here. * gcc.dg/analyzer/deref-before-check-pr77425.c: Moved to... * c-c++-common/analyzer/deref-before-check-pr77425.c: ...here. * gcc.dg/analyzer/exec-1.c: Moved to... * c-c++-common/analyzer/exec-1.c: ...here. * gcc.dg/analyzer/feasibility-3.c: Moved to... * c-c++-common/analyzer/feasibility-3.c: ...here. * gcc.dg/analyzer/fields.c: Moved to... * c-c++-common/analyzer/fields.c: ...here. * gcc.dg/analyzer/function-ptr-5.c: Moved to... * c-c++-common/analyzer/function-ptr-5.c: ...here. * gcc.dg/analyzer/infinite-recursion-pr108524-1.c: Moved to... * c-c++-common/analyzer/infinite-recursion-pr108524-1.c: ...here. * gcc.dg/analyzer/infinite-recursion-pr108524-2.c: Moved to... * c-c++-common/analyzer/infinite-recursion-pr108524-2.c: ...here. * gcc.dg/analyzer/infinite-recursion-pr108524-qobject-json-parser.c: Moved to... * c-c++-common/analyzer/infinite-recursion-pr108524-qobject-json-parser.c: ...here. * gcc.dg/analyzer/init.c: Moved to... * c-c++-common/analyzer/init.c: ...here. * gcc.dg/analyzer/inlining-3-multiline.c: Moved to... * c-c++-common/analyzer/inlining-3-multiline.c: ...here. * gcc.dg/analyzer/inlining-3.c: Moved to... * c-c++-common/analyzer/inlining-3.c: ...here. * gcc.dg/analyzer/inlining-4-multiline.c: Moved to... * c-c++-common/analyzer/inlining-4-multiline.c: ...here. * gcc.dg/analyzer/inlining-4.c: Moved to... * c-c++-common/analyzer/inlining-4.c: ...here. * gcc.dg/analyzer/leak-pr105906.c: Moved to... * c-c++-common/analyzer/leak-pr105906.c: ...here. * gcc.dg/analyzer/leak-pr108045-with-call-summaries.c: Moved to... * c-c++-common/analyzer/leak-pr108045-with-call-summaries.c: ...here. * gcc.dg/analyzer/leak-pr108045-without-call-summaries.c: Moved to... * c-c++-common/analyzer/leak-pr108045-without-call-summaries.c: ...here. * gcc.dg/analyzer/leak-pr109059-1.c: Moved to... * c-c++-common/analyzer/leak-pr109059-1.c: ...here. * gcc.dg/analyzer/leak-pr109059-2.c: Moved to... * c-c++-common/analyzer/leak-pr109059-2.c: ...here. * gcc.dg/analyzer/malloc-2.c: Moved to... * c-c++-common/analyzer/malloc-2.c: ...here. * gcc.dg/analyzer/memcpy-2.c: Moved to... * c-c++-common/analyzer/memcpy-2.c: ...here. * gcc.dg/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early-O2.c: Moved to... * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early-O2.c: ...here. * gcc.dg/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c: Moved to... * c-c++-common/analyzer/null-deref-pr108251-smp_fetch_ssl_fc_has_early.c: ...here. * gcc.dg/analyzer/null-deref-pr108806-qemu.c: Moved to... * c-c++-common/analyzer/null-deref-pr108806-qemu.c: ...here. * gcc.dg/analyzer/null-deref-pr108830.c: Moved to... * c-c++-common/analyzer/null-deref-pr108830.c: ...here. * gcc.dg/analyzer/pr101962.c: Moved to... * c-c++-common/analyzer/pr101962.c: ...here. * gcc.dg/analyzer/pr103217-2.c: Moved to... * c-c++-common/analyzer/pr103217-2.c: ...here. * gcc.dg/analyzer/pr103217.c: Moved to... * c-c++-common/analyzer/pr103217.c: ...here. * gcc.dg/analyzer/pr104029.c: Moved to... * c-c++-common/analyzer/pr104029.c: ...here. * gcc.dg/analyzer/pr104062.c: Moved to... * c-c++-common/analyzer/pr104062.c: ...here. * gcc.dg/analyzer/pr105783.c: Moved to... * c-c++-common/analyzer/pr105783.c: ...here. * gcc.dg/analyzer/pr107345.c: Moved to... * c-c++-common/analyzer/pr107345.c: ...here. * gcc.dg/analyzer/pr93695-1.c: Moved to... * c-c++-common/analyzer/pr93695-1.c: ...here. * gcc.dg/analyzer/pr94596.c: Moved to... * c-c++-common/analyzer/pr94596.c: ...here. * gcc.dg/analyzer/pr94839.c: Moved to... * c-c++-common/analyzer/pr94839.c: ...here. * gcc.dg/analyzer/pr95152-4.c: C only. * gcc.dg/analyzer/pr95152-5.c: C only. * gcc.dg/analyzer/pr95240.c: Moved to... * c-c++-common/analyzer/pr95240.c: ...here. * gcc.dg/analyzer/pr96639.c: Moved to... * c-c++-common/analyzer/pr96639.c: ...here. * gcc.dg/analyzer/pr96653.c: Moved to... * c-c++-common/analyzer/pr96653.c: ...here. * gcc.dg/analyzer/pr96792.c: Moved to... * c-c++-common/analyzer/pr96792.c: ...here. * gcc.dg/analyzer/pr96841.c: Moved to... * c-c++-common/analyzer/pr96841.c: ...here. * gcc.dg/analyzer/pr98564.c: Moved to... * c-c++-common/analyzer/pr98564.c: ...here. * gcc.dg/analyzer/pr98628.c: Moved to... * c-c++-common/analyzer/pr98628.c: ...here. * gcc.dg/analyzer/pr98969.c: Moved to... * c-c++-common/analyzer/pr98969.c: ...here. * gcc.dg/analyzer/pr99193-2.c: Moved to... * c-c++-common/analyzer/pr99193-2.c: ...here. * gcc.dg/analyzer/pr99193-3.c: Moved to... * c-c++-common/analyzer/pr99193-3.c: ...here. * gcc.dg/analyzer/pr99716-1.c: Moved to... * c-c++-common/analyzer/pr99716-1.c: ...here. * gcc.dg/analyzer/pr99774-1.c: Moved to... * c-c++-common/analyzer/pr99774-1.c: ...here. * gcc.dg/analyzer/realloc-1.c: Moved to... * c-c++-common/analyzer/realloc-1.c: ...here. * gcc.dg/analyzer/realloc-2.c: Moved to... * c-c++-common/analyzer/realloc-2.c: ...here. * gcc.dg/analyzer/realloc-3.c: Moved to... * c-c++-common/analyzer/realloc-3.c: ...here. * gcc.dg/analyzer/realloc-4.c: Moved to... * c-c++-common/analyzer/realloc-4.c: ...here. * gcc.dg/analyzer/realloc-5.c: Moved to... * c-c++-common/analyzer/realloc-5.c: ...here. * gcc.dg/analyzer/realloc-pr110014.c: Moved to... * c-c++-common/analyzer/realloc-pr110014.c: ...here. * gcc.dg/analyzer/snprintf-concat.c: Moved to... * c-c++-common/analyzer/snprintf-concat.c: ...here. * gcc.dg/analyzer/sock-1.c: Moved to... * c-c++-common/analyzer/sock-1.c: ...here. * gcc.dg/analyzer/sprintf-concat.c: Moved to... * c-c++-common/analyzer/sprintf-concat.c: ...here. * gcc.dg/analyzer/string-ops-concat-pair.c: Moved to... * c-c++-common/analyzer/string-ops-concat-pair.c: ...here. * gcc.dg/analyzer/string-ops-dup.c: Moved to... * c-c++-common/analyzer/string-ops-dup.c: ...here. * gcc.dg/analyzer/switch-enum-pr105273-git-vreportf-2.c: Moved to... * c-c++-common/analyzer/switch-enum-pr105273-git-vreportf-2.c: ...here. * gcc.dg/analyzer/symbolic-12.c: Moved to... * c-c++-common/analyzer/symbolic-12.c: ...here. * gcc.dg/analyzer/uninit-alloca.c: Moved to... * c-c++-common/analyzer/uninit-alloca.c: ...here. * gcc.dg/analyzer/untracked-2.c: Moved to... * c-c++-common/analyzer/untracked-2.c: ...here. * gcc.dg/analyzer/vasprintf-1.c: Moved to... * c-c++-common/analyzer/vasprintf-1.c: ...here. * gcc.dg/analyzer/write-to-const-1.c: Moved to... * c-c++-common/analyzer/write-to-const-1.c: ...here. * gcc.dg/analyzer/write-to-function-1.c: C only. * gcc.dg/analyzer/write-to-string-literal-1.c: Moved to... * c-c++-common/analyzer/write-to-string-literal-1.c: ...here. * gcc.dg/analyzer/write-to-string-literal-4-disabled.c: Moved to... * c-c++-common/analyzer/write-to-string-literal-4-disabled.c: ...here. * gcc.dg/analyzer/write-to-string-literal-5.c: Moved to... * c-c++-common/analyzer/write-to-string-literal-5.c: ...here. * g++.dg/analyzer/analyzer.exp: Now also run tests under c-c++-common/analyzer. * gcc.dg/analyzer/analyzer-decls.h: Add NULL definition. * gcc.dg/analyzer/analyzer.exp: Now also run tests under c-c++-common/analyzer. * gcc.dg/analyzer/pr104369-1.c: C only. * gcc.dg/analyzer/pr104369-2.c: Likewise. * gcc.dg/analyzer/pr93355-localealias-feasibility-2.c: Likewise. * gcc.dg/analyzer/sprintf-1.c: Split into C-only and C++-friendly bits. * gcc.dg/analyzer/allocation-size-multiline-1.c: Removed. * gcc.dg/analyzer/allocation-size-multiline-2.c: Removed. * gcc.dg/analyzer/allocation-size-multiline-3.c: Removed. * gcc.dg/analyzer/data-model-11.c: Removed. * gcc.dg/analyzer/pr61861.c: C only. * gcc.dg/analyzer/pr93457.c: Removed. * gcc.dg/analyzer/pr97568.c: Removed. * gcc.dg/analyzer/write-to-string-literal-4.c: Removed. * c-c++-common/analyzer/allocation-size-multiline-1.c: New test. * c-c++-common/analyzer/allocation-size-multiline-2.c: New test. * c-c++-common/analyzer/allocation-size-multiline-3.c: New test. * c-c++-common/analyzer/data-model-11.c: New test. * c-c++-common/analyzer/pr93457.c: New test. * c-c++-common/analyzer/pr97568.c: New test. * c-c++-common/analyzer/sprintf-2.c: C++-friendly bit of previous gcc.dg/analyzer/sprintf-1.c. * c-c++-common/analyzer/write-to-string-literal-4.c: New test.
2023-08-27Daily bump.GCC Administrator4-1/+58
2023-08-26Fortran: Supply a missing dereference [PR92586]Paul Thomas2-1/+63
2023-08-26 Paul Thomas <pault@gcc.gnu.org> gcc/fortran PR fortran/92586 * trans-expr.cc (gfc_trans_arrayfunc_assign): Supply a missing dereference for the call to gfc_deallocate_alloc_comp_no_caf. gcc/testsuite/ PR fortran/92586 * gfortran.dg/pr92586.f90 : New test
2023-08-26RISC-V: Support LEN_FOLD_EXTRACT_LAST auto-vectorizationJuzhe-Zhong32-6/+478
Consider this following case: int __attribute__ ((noinline, noclone)) condition_reduction (int *a, int min_v) { int last = 66; /* High start value. */ for (int i = 0; i < 4; i++) if (a[i] < min_v) last = i; return last; } --param=riscv-autovec-preference=fixed-vlmax --param=riscv-autovec-lmul=m8 condition_reduction: vsetvli a4,zero,e32,m8,ta,ma li a5,32 vmv.v.x v8,a1 vl8re32.v v0,0(a0) vid.v v16 vmslt.vv v0,v0,v8 vsetvli zero,a5,e8,m2,ta,ma vcpop.m a5,v0 beq a5,zero,.L2 addi a5,a5,-1 vsetvli a4,zero,e32,m8,ta,ma vcompress.vm v8,v16,v0 vslidedown.vx v8,v8,a5 vmv.x.s a0,v8 ret .L2: li a0,66 ret --param=riscv-autovec-preference=scalable condition_reduction: csrr a6,vlenb mv a2,a0 li a3,32 li a0,66 srli a6,a6,2 vsetvli a4,zero,e32,m1,ta,ma vmv.v.x v4,a1 vid.v v1 .L4: vsetvli a5,a3,e8,mf4,tu,mu vsetvli zero,a5,e32,m1,ta,ma ----> redundant vsetvl vle32.v v0,0(a2) vsetvli a4,zero,e32,m1,ta,ma slli a1,a5,2 vmv.v.x v2,a6 vmslt.vv v0,v0,v4 sub a3,a3,a5 vmv1r.v v3,v1 vadd.vv v1,v1,v2 vsetvli zero,a5,e8,mf4,ta,ma vcpop.m a5,v0 beq a5,zero,.L3 addi a5,a5,-1 vsetvli a4,zero,e32,m1,ta,ma vcompress.vm v2,v3,v0 vslidedown.vx v2,v2,a5 vmv.x.s a0,v2 .L3: sext.w a0,a0 add a2,a2,a1 bne a3,zero,.L4 ret There is a redundant vsetvli instruction in VLA vectorized codes which is the VSETVL PASS issue. vsetvl issue is not included in this patch but will be fixed soon. gcc/ChangeLog: * config/riscv/autovec.md (len_fold_extract_last_<mode>): New pattern. * config/riscv/riscv-protos.h (enum insn_type): New enum. (expand_fold_extract_last): New function. * config/riscv/riscv-v.cc (emit_nonvlmax_slide_insn): Ditto. (emit_cpop_insn): Ditto. (emit_nonvlmax_compress_insn): Ditto. (expand_fold_extract_last): Ditto. * config/riscv/vector.md: Fix vcpop.m ratio demand. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/reduc/extract_last-1.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-11.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-12.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-13.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-14.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-2.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-3.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-4.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-5.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-6.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-7.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-8.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last-9.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-1.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-10.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-11.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-12.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-13.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-14.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-2.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-3.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-4.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-5.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-6.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-7.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-8.c: New test. * gcc.target/riscv/rvv/autovec/reduc/extract_last_run-9.c: New test.
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