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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2023-08-28 15:13:53 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-28 15:13:53 -0600 |
| commit | cf64ab18e3f820376ff20c663c7c7bf1af290f02 (patch) | |
| tree | 4852d8c6f59b30e43fc680c3fd312cfc4b31a3ea | |
| parent | c2d04dd659c499d8df19f68d0602ad4c7d7065c2 (diff) | |
| download | gcc-cf64ab18e3f820376ff20c663c7c7bf1af290f02.zip gcc-cf64ab18e3f820376ff20c663c7c7bf1af290f02.tar.gz gcc-cf64ab18e3f820376ff20c663c7c7bf1af290f02.tar.bz2 | |
RISC-V: Fix documentation of __builtin_riscv_pause
This built-in does not imply the 'Xgnuzihintpausestate' extension.
It does not change architectural state (because all HINTs are prohibited
from doing that).
gcc/ChangeLog:
* doc/extend.texi: Fix the description of __builtin_riscv_pause.
| -rw-r--r-- | gcc/doc/extend.texi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 2632867..174d785 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -21607,9 +21607,9 @@ Returns the value that is currently set in the @samp{tp} register. @enddefbuiltin @defbuiltin{void __builtin_riscv_pause (void)} -Generates the @code{pause} (hint) machine instruction. This implies the -Xgnuzihintpausestate extension, which redefines the @code{pause} instruction to -change architectural state. +Generates the @code{pause} (hint) machine instruction. If the target implements +the Zihintpause extension, it indicates that the current hart should be +temporarily paused or slowed down. @enddefbuiltin @node RISC-V Vector Intrinsics |