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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-08-29 14:48:32 +0800
committerLehua Ding <lehua.ding@rivai.ai>2023-08-29 15:02:06 +0800
commit97aafa9cbb68ffa23aa9f018cc5cb30648a72427 (patch)
tree42310179cd51ac06145c28ebe5f1b7c6323d9c15
parentacaf9e333dbc2eb811848c169f95ec7a8ca0e2e7 (diff)
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vect test: Remove xfail for riscv
We are planning to enable "vect" testsuite with scalable vector auto-vectorization. This case XPASS: XPASS: gcc.dg/vect/no-scevccp-outer-12.c scan-tree-dump-times vect "OUTER LOOP VECTORIZED." 1 like ARM SVE. gcc/testsuite/ChangeLog: * gcc.dg/vect/no-scevccp-outer-12.c: Add riscv xfail.
-rw-r--r--gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c
index e9ec4ca..c2d3031 100644
--- a/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c
+++ b/gcc/testsuite/gcc.dg/vect/no-scevccp-outer-12.c
@@ -47,4 +47,4 @@ int main (void)
}
/* Until we support multiple types in the inner loop */
-/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! aarch64*-*-* } } } } */
+/* { dg-final { scan-tree-dump-times "OUTER LOOP VECTORIZED." 1 "vect" { xfail { ! { aarch64*-*-* riscv*-*-* } } } } } */