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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-09-09 17:59:14 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-09 17:59:14 +0000 |
| commit | dc333d8ff60909dbed89126443e3024f1592f8a4 (patch) | |
| tree | 8cb63764fe33068c8b53a63d5441237984aa4aa7 /gcc/config | |
| parent | 50b3f54d551787e0a066451ef60ef3b055a893e6 (diff) | |
| download | gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.zip gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.tar.gz gcc-dc333d8ff60909dbed89126443e3024f1592f8a4.tar.bz2 | |
Remove AND_HARD_REG_SET
Use "x &= y" instead of "AND_HARD_REG_SET (x, y)" (or just "x & y"
if the result is a temporary).
2019-09-09 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* hard-reg-set.h (HARD_REG_SET::operator&): New function.
(HARD_REG_SET::operator&): Likewise.
(AND_HARD_REG_SET): Delete.
* caller-save.c (setup_save_areas): Use "&" instead of
AND_HARD_REG_SET.
(save_call_clobbered_regs): Likewise.
* config/gcn/gcn.c (gcn_md_reorg): Likewise.
* config/m32c/m32c.c (reduce_class): Likewise.
* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
* final.c (get_call_reg_set_usage): Likewise.
* ira-color.c (add_allocno_hard_regs_to_forest): Likewise.
(setup_left_conflict_sizes_p): Likewise.
* ira-conflicts.c (print_allocno_conflicts): Likewise.
(ira_build_conflicts): Likewise.
* ira-costs.c (restrict_cost_classes): Likewise.
* ira.c (setup_stack_reg_pressure_class, setup_class_translate_array)
(setup_reg_class_relations): Likewise.
* reginfo.c (init_reg_sets_1, record_subregs_of_mode): Likewise.
* reload1.c (maybe_fix_stack_asms, finish_spills): Likewise.
* resource.c (find_dead_or_set_registers): Likewise.
* sel-sched.c (mark_unavailable_hard_regs): Likewise.
From-SVN: r275530
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/gcn/gcn.c | 12 | ||||
| -rw-r--r-- | gcc/config/m32c/m32c.c | 3 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 6 |
3 files changed, 6 insertions, 15 deletions
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 548ab17..2c6c872 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -4552,9 +4552,7 @@ gcn_md_reorg (void) && prev_insn->unit == UNIT_VECTOR && gcn_vmem_insn_p (itype)) { - HARD_REG_SET regs; - regs = prev_insn->writes; - AND_HARD_REG_SET (regs, ireads); + HARD_REG_SET regs = prev_insn->writes & ireads; if (hard_reg_set_intersect_p (regs, reg_class_contents[(int) SGPR_REGS])) nops_rqd = 5 - prev_insn->age; @@ -4582,9 +4580,7 @@ gcn_md_reorg (void) && prev_insn->unit == UNIT_VECTOR && get_attr_laneselect (insn) == LANESELECT_YES) { - HARD_REG_SET regs; - regs = prev_insn->writes; - AND_HARD_REG_SET (regs, ireads); + HARD_REG_SET regs = prev_insn->writes & ireads; if (hard_reg_set_intersect_p (regs, reg_class_contents[(int) SGPR_REGS]) || hard_reg_set_intersect_p @@ -4598,9 +4594,7 @@ gcn_md_reorg (void) && prev_insn->unit == UNIT_VECTOR && itype == TYPE_VOP_DPP) { - HARD_REG_SET regs; - regs = prev_insn->writes; - AND_HARD_REG_SET (regs, ireads); + HARD_REG_SET regs = prev_insn->writes & ireads; if (hard_reg_set_intersect_p (regs, reg_class_contents[(int) VGPR_REGS])) nops_rqd = 2 - prev_insn->age; diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c index 4e18287..d89064a 100644 --- a/gcc/config/m32c/m32c.c +++ b/gcc/config/m32c/m32c.c @@ -341,8 +341,7 @@ reduce_class (reg_class_t original_class, reg_class_t limiting_class, if (original_class == limiting_class) return original_class; - cc = reg_class_contents[original_class]; - AND_HARD_REG_SET (cc, reg_class_contents[limiting_class]); + cc = reg_class_contents[original_class] & reg_class_contents[limiting_class]; for (i = 0; i < LIM_REG_CLASSES; i++) { diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8193c6b..03349e8 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -21107,10 +21107,8 @@ rs6000_register_move_cost (machine_mode mode, Do this first so we give best-case answers for union classes containing both gprs and vsx regs. */ HARD_REG_SET to_vsx, from_vsx; - to_vsx = reg_class_contents[to]; - AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]); - from_vsx = reg_class_contents[from]; - AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]); + to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS]; + from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; if (!hard_reg_set_empty_p (to_vsx) && !hard_reg_set_empty_p (from_vsx) && (TARGET_VSX |