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| author | Richard Earnshaw <rearnsha@arm.com> | 2013-09-10 16:46:55 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@gcc.gnu.org> | 2013-09-10 16:46:55 +0000 |
| commit | d742ff4ba1609fe71d0a9396483b95d375e4599a (patch) | |
| tree | 0de0c179386f1b6a4d999a5b2ffd8cee0ff882fd /gcc/config | |
| parent | 1329f0c4e27f29cef728a9ab0329e1dd287a7812 (diff) | |
| download | gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.zip gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.tar.gz gcc-d742ff4ba1609fe71d0a9396483b95d375e4599a.tar.bz2 | |
re PR target/58361 (Wrong floating point code generated for ARM target)
PR target/58361
* arm/vfp.md (combine_vcvt_f32_<FCVTI32typename>): Fix pattern to
support conditional execution.
(combine_vcvt_f64_<FCVTI32typename>): Likewise.
From-SVN: r202475
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/vfp.md | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 9318e49..0b10c13 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1217,19 +1217,20 @@ (set_attr "type" "fcmpd")] ) -;; Fixed point to floating point conversions. +;; Fixed point to floating point conversions. (define_code_iterator FCVT [unsigned_float float]) (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) (define_insn "*combine_vcvt_f32_<FCVTI32typename>" [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" - "vcvt.f32.<FCVTI32typename>\\t%0, %1, %v2" - [(set_attr "predicable" "no") - (set_attr "type" "f_cvti2f")] + "vcvt%?.f32.<FCVTI32typename>\\t%0, %1, %v2" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvti2f")] ) ;; Not the ideal way of implementing this. Ideally we would be able to split @@ -1237,17 +1238,19 @@ (define_insn "*combine_vcvt_f64_<FCVTI32typename>" [(set (match_operand:DF 0 "s_register_operand" "=x,x,w") (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))] - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math && !TARGET_VFP_SINGLE" "@ - vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2 - vmov.f32\\t%0, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2 - vmov.f64\\t%P0, %1, %1\;vcvt.f64.<FCVTI32typename>\\t%P0, %P0, %v2" - [(set_attr "predicable" "no") - (set_attr "type" "f_cvti2f") - (set_attr "length" "8")] + vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 + vmov%?.f32\\t%0, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2 + vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.<FCVTI32typename>\\t%P0, %P0, %v2" + [(set_attr "predicable" "yes") + (set_attr "ce_count" "2") + (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvti2f") + (set_attr "length" "8")] ) ;; Store multiple insn used in function prologue. |