From d742ff4ba1609fe71d0a9396483b95d375e4599a Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Tue, 10 Sep 2013 16:46:55 +0000 Subject: re PR target/58361 (Wrong floating point code generated for ARM target) PR target/58361 * arm/vfp.md (combine_vcvt_f32_): Fix pattern to support conditional execution. (combine_vcvt_f64_): Likewise. From-SVN: r202475 --- gcc/config/arm/vfp.md | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) (limited to 'gcc/config') diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 9318e49..0b10c13 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -1217,19 +1217,20 @@ (set_attr "type" "fcmpd")] ) -;; Fixed point to floating point conversions. +;; Fixed point to floating point conversions. (define_code_iterator FCVT [unsigned_float float]) (define_code_attr FCVTI32typename [(unsigned_float "u32") (float "s32")]) (define_insn "*combine_vcvt_f32_" [(set (match_operand:SF 0 "s_register_operand" "=t") (mult:SF (FCVT:SF (match_operand:SI 1 "s_register_operand" "0")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" - "vcvt.f32.\\t%0, %1, %v2" - [(set_attr "predicable" "no") - (set_attr "type" "f_cvti2f")] + "vcvt%?.f32.\\t%0, %1, %v2" + [(set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvti2f")] ) ;; Not the ideal way of implementing this. Ideally we would be able to split @@ -1237,17 +1238,19 @@ (define_insn "*combine_vcvt_f64_" [(set (match_operand:DF 0 "s_register_operand" "=x,x,w") (mult:DF (FCVT:DF (match_operand:SI 1 "s_register_operand" "r,t,r")) - (match_operand 2 + (match_operand 2 "const_double_vcvt_power_of_two_reciprocal" "Dt,Dt,Dt")))] - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math && !TARGET_VFP_SINGLE" "@ - vmov.f32\\t%0, %1\;vcvt.f64.\\t%P0, %P0, %v2 - vmov.f32\\t%0, %1\;vcvt.f64.\\t%P0, %P0, %v2 - vmov.f64\\t%P0, %1, %1\;vcvt.f64.\\t%P0, %P0, %v2" - [(set_attr "predicable" "no") - (set_attr "type" "f_cvti2f") - (set_attr "length" "8")] + vmov%?.f32\\t%0, %1\;vcvt%?.f64.\\t%P0, %P0, %v2 + vmov%?.f32\\t%0, %1\;vcvt%?.f64.\\t%P0, %P0, %v2 + vmov%?.f64\\t%P0, %1, %1\;vcvt%?.f64.\\t%P0, %P0, %v2" + [(set_attr "predicable" "yes") + (set_attr "ce_count" "2") + (set_attr "predicable_short_it" "no") + (set_attr "type" "f_cvti2f") + (set_attr "length" "8")] ) ;; Store multiple insn used in function prologue. -- cgit v1.1