diff options
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 9 |
2 files changed, 9 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c8b67cd..2802cdf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-09-28 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_print_operand_address_as): Do not check + index when encoding %esp as %rsp to avoid 0x67 prefix. + 2017-09-28 Sergey Shalnov <Sergey.Shalnov@intel.com> * config/i386/i386.md (*movsf_internal, *movdf_internal): diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 63db7ac..e282546 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19953,12 +19953,11 @@ ix86_print_operand_address_as (FILE *file, rtx addr, code = 'k'; } - /* Since the upper 32 bits of RSP are always zero for x32, we can - encode %esp as %rsp to avoid 0x67 prefix if there is no index or - base register. */ + /* Since the upper 32 bits of RSP are always zero for x32, + we can encode %esp as %rsp to avoid 0x67 prefix if + there is no index register. */ if (TARGET_X32 && Pmode == SImode - && ((!index && base && REG_P (base) && REGNO (base) == SP_REG) - || (!base && index && REGNO (index) == SP_REG))) + && !index && base && REG_P (base) && REGNO (base) == SP_REG) code = 'q'; if (ASSEMBLER_DIALECT == ASM_ATT) |