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authorPeter Bergner <bergner@vnet.ibm.com>2016-07-01 08:51:35 -0500
committerPeter Bergner <bergner@gcc.gnu.org>2016-07-01 08:51:35 -0500
commit2c1e49643bcc316dea32af6ed3e60bd4f890f291 (patch)
tree8b1a6f3dd33ac94bb064326d2fec9f351c5067b2 /gcc/config
parent22e1cb39f3a5f083f4c10852c602d65e10292d78 (diff)
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re PR target/71698 (ICE related to decimal float when compiling with -mcpu=power9)
gcc/ PR target/71698 * config/rs6000/rs6000.c (rs6000_secondary_reload_simple_move): Disallow TDmode values. gcc/testsuite/ PR target/71698 * gcc.target/powerpc/pr71698.c: New test. From-SVN: r237911
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/rs6000/rs6000.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a34f287..dd77e1b1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -19194,7 +19194,8 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
simple move insns are issued. At present, 32-bit integers are not allowed
in FPR/VSX registers. Single precision binary floating is not a simple
move because we need to convert to the single precision memory layout.
- The 4-byte SDmode can be moved. */
+ The 4-byte SDmode can be moved. TDmode values are disallowed since they
+ need special direct move handling, which we do not support yet. */
size = GET_MODE_SIZE (mode);
if (TARGET_DIRECT_MOVE
&& ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))
@@ -19202,7 +19203,7 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
|| (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
return true;
- else if (TARGET_DIRECT_MOVE_128 && size == 16
+ else if (TARGET_DIRECT_MOVE_128 && size == 16 && mode != TDmode
&& ((to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
|| (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)))
return true;