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| author | Roger Sayle <roger@nextmovesoftware.com> | 2022-03-11 17:57:12 +0000 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-03-11 17:57:12 +0000 |
| commit | 251ea6dfbdb4448875e41081682bb3aa451b5729 (patch) | |
| tree | 1297567f040ce10d1d026251a788f7abf62e896f /gcc/config | |
| parent | c5288df751f9ecd11898dec5f2a7b6b03267f79e (diff) | |
| download | gcc-251ea6dfbdb4448875e41081682bb3aa451b5729.zip gcc-251ea6dfbdb4448875e41081682bb3aa451b5729.tar.gz gcc-251ea6dfbdb4448875e41081682bb3aa451b5729.tar.bz2 | |
PR tree-optimization/98335: New peephole2 xorl;movb -> movzbl
This patch is the backend piece of my proposed fix to PR tree-opt/98335,
to allow C++ partial struct initialization to be as efficient/optimized
as full struct initialization.
With the middle-end patch just posted to gcc-patches, the test case
in the PR compiles on x86_64-pc-linux-gnu with -O2 to:
xorl %eax, %eax
movb c(%rip), %al
ret
with this additional peephole2 (actually four peephole2s):
movzbl c(%rip), %eax
ret
2022-03-11 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR tree-optimization/98335
* config/i386/i386.md (peephole2): Eliminate redundant insv.
Combine movl followed by movb. Transform xorl followed by
a suitable movb or movw into the equivalent movz[bw]l.
gcc/testsuite/ChangeLog
PR tree-optimization/98335
* g++.target/i386/pr98335.C: New test case.
* gcc.target/i386/pr98335.c: New test case.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d15170e..c8fbf60 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3180,6 +3180,38 @@ (const_int 8)) (subreg:SWI248 (match_dup 1) 0))]) +;; Eliminate redundant insv, e.g. xorl %eax,%eax; movb $0, %ah +(define_peephole2 + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (set (zero_extract:SWI248 (match_operand:SWI248 1 "general_reg_operand") + (const_int 8) + (const_int 8)) + (const_int 0))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))])]) + +;; Combine movl followed by movb. +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_operand:SWI48 1 "const_int_operand")) + (set (zero_extract:SWI248 (match_operand:SWI248 2 "general_reg_operand") + (const_int 8) + (const_int 8)) + (match_operand:SWI248 3 "const_int_operand"))] + "REGNO (operands[0]) == REGNO (operands[2])" + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_dup 4))] +{ + HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~(HOST_WIDE_INT)0xff00; + tmp |= (INTVAL (operands[3]) & 0xff) << 8; + operands[4] = gen_int_mode (tmp, <SWI48:MODE>mode); +}) + + (define_code_iterator any_extract [sign_extract zero_extract]) (define_insn "*insvqi_2" @@ -4276,6 +4308,24 @@ [(set_attr "isa" "*,avx512dq,avx512dq") (set_attr "type" "imovx,mskmov,mskmov") (set_attr "mode" "SI,QI,QI")]) + +;; Transform xorl; mov[bw] (set strict_low_part) into movz[bw]l. +(define_peephole2 + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (set (strict_low_part (match_operand:SWI12 1 "general_reg_operand")) + (match_operand:SWI12 2 "nonimmediate_operand"))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))]) + +;; Likewise, but preserving FLAGS_REG. +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") (const_int 0)) + (set (strict_low_part (match_operand:SWI12 1 "general_reg_operand")) + (match_operand:SWI12 2 "nonimmediate_operand"))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))]) ;; Sign extension instructions |