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| author | Xianmiao Qu <cooper.qu@linux.alibaba.com> | 2024-09-18 07:28:44 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-18 07:29:36 -0600 |
| commit | ec34a4481b63bb5028b2a8c61322a7a3d362b27c (patch) | |
| tree | cce177fc26be885f10a05ff4c398e033874ab262 /gcc/config/riscv | |
| parent | 0756f335fb6e455641850a76e68f892f1f82ada2 (diff) | |
| download | gcc-ec34a4481b63bb5028b2a8c61322a7a3d362b27c.zip gcc-ec34a4481b63bb5028b2a8c61322a7a3d362b27c.tar.gz gcc-ec34a4481b63bb5028b2a8c61322a7a3d362b27c.tar.bz2 | |
[PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.
The Combine Pass may generate zero_extract instructions that are out of range.
Drawing from other architectures like AArch64, we should impose restrictions
on the "*th_extu<mode>4" pattern.
gcc/
* config/riscv/thead.md (*th_extu<mode>4): Fix th.extu
operands exceeding range on rv32.
gcc/testsuite/
* gcc.target/riscv/xtheadbb-extu-4.c: New.
Diffstat (limited to 'gcc/config/riscv')
| -rw-r--r-- | gcc/config/riscv/thead.md | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 2a3af76..7a76cc8 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -85,7 +85,9 @@ (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") (match_operand 2 "const_int_operand") (match_operand 3 "const_int_operand")))] - "TARGET_XTHEADBB" + "TARGET_XTHEADBB + && (UINTVAL (operands[2]) + UINTVAL (operands[3]) + <= GET_MODE_BITSIZE (<MODE>mode))" { operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3]) - 1); return "th.extu\t%0,%1,%2,%3"; |