diff options
| author | Bohan Lei <garthlei@linux.alibaba.com> | 2024-09-18 07:20:23 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-18 07:22:04 -0600 |
| commit | 0756f335fb6e455641850a76e68f892f1f82ada2 (patch) | |
| tree | f794de0fc3684b34c19c12173ce82555f34de1ea /gcc/config/riscv | |
| parent | 5c8f9f4d4cebabf85e68c5bdbe2d4ee6646edc7c (diff) | |
| download | gcc-0756f335fb6e455641850a76e68f892f1f82ada2.zip gcc-0756f335fb6e455641850a76e68f892f1f82ada2.tar.gz gcc-0756f335fb6e455641850a76e68f892f1f82ada2.tar.bz2 | |
[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx
The RISC-V vector machine description relies on the helper function
`sew64_scalar_helper` to emit actual insns for the DI variants of
vssub.vx and vssubu.vx. This works with vssub.vx, but can cause
problems with vssubu.vx with the scalar operand being constant zero,
because `has_vi_variant_p` returns false, and the operand will be taken
without being loaded into a reg. The attached testcases can cause an
internal compiler error as a result.
Allowing a constant zero operand in those insns seems to be a simple
solution that only affects minimum existing code.
gcc/ChangeLog:
* config/riscv/vector.md: Allow zero operand for DI variants of
vssubu.vx
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssubu-1.c: New test.
* gcc.target/riscv/rvv/base/vssubu-2.c: New test.
Diffstat (limited to 'gcc/config/riscv')
| -rw-r--r-- | gcc/config/riscv/vector.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d067732..92e3061 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4400,10 +4400,10 @@ (sat_int_minus_binop:VI_D (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VI_D - (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))) + (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" - "v<insn>.vx\t%0,%3,%4%p1" + "v<insn>.vx\t%0,%3,%z4%p1" [(set_attr "type" "<int_binop_insn_type>") (set_attr "mode" "<MODE>")]) @@ -4422,10 +4422,10 @@ (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr") (vec_duplicate:VI_D (sign_extend:<VEL> - (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))) + (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")))) (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && !TARGET_64BIT" - "v<insn>.vx\t%0,%3,%4%p1" + "v<insn>.vx\t%0,%3,%z4%p1" [(set_attr "type" "<int_binop_insn_type>") (set_attr "mode" "<MODE>")]) |