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authorJin Ma <jinma@linux.alibaba.com>2024-09-18 08:56:23 -0600
committerJeff Law <jlaw@ventanamicro.com>2024-09-18 08:57:27 -0600
commit85fcf740342e308da4776a45a4cd726987725a6a (patch)
treec292a3fba075cd1545fc16fbd8022dd2543b84b7 /gcc/config/riscv
parent4b7e6d5faa137f18a36d8c6323a8640e61ee48f1 (diff)
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[PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.
gcc/ChangeLog: * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32. gcc/testsuite/ChangeLog: * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
Diffstat (limited to 'gcc/config/riscv')
-rw-r--r--gcc/config/riscv/riscv.md16
1 files changed, 9 insertions, 7 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index fd1cbeb..0410d99 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -56,6 +56,8 @@
UNSPEC_FLT_QUIET
UNSPEC_FLE_QUIET
UNSPEC_COPYSIGN
+ UNSPEC_FMV_X_W
+ UNSPEC_FMVH_X_D
UNSPEC_RINT
UNSPEC_ROUND
UNSPEC_FLOOR
@@ -2626,8 +2628,9 @@
(define_insn "movsidf2_low_rv32"
[(set (match_operand:SI 0 "register_operand" "= r")
- (truncate:SI
- (match_operand:DF 1 "register_operand" "zmvf")))]
+ (unspec:SI
+ [(match_operand:DF 1 "register_operand" "zmvf")]
+ UNSPEC_FMV_X_W))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmv.x.w\t%0,%1"
[(set_attr "move_type" "fmove")
@@ -2636,11 +2639,10 @@
(define_insn "movsidf2_high_rv32"
- [(set (match_operand:SI 0 "register_operand" "= r")
- (truncate:SI
- (lshiftrt:DF
- (match_operand:DF 1 "register_operand" "zmvf")
- (const_int 32))))]
+ [(set (match_operand:SI 0 "register_operand" "= r")
+ (unspec:SI
+ [(match_operand:DF 1 "register_operand" "zmvf")]
+ UNSPEC_FMVH_X_D))]
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvh.x.d\t%0,%1"
[(set_attr "move_type" "fmove")