From 85fcf740342e308da4776a45a4cd726987725a6a Mon Sep 17 00:00:00 2001
From: Jin Ma <jinma@linux.alibaba.com>
Date: Wed, 18 Sep 2024 08:56:23 -0600
Subject: [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI
 pattern in the Zfa extension on rv32.

gcc/ChangeLog:

	* config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
---
 gcc/config/riscv/riscv.md | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'gcc/config/riscv')

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index fd1cbeb..0410d99 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -56,6 +56,8 @@
   UNSPEC_FLT_QUIET
   UNSPEC_FLE_QUIET
   UNSPEC_COPYSIGN
+  UNSPEC_FMV_X_W
+  UNSPEC_FMVH_X_D
   UNSPEC_RINT
   UNSPEC_ROUND
   UNSPEC_FLOOR
@@ -2626,8 +2628,9 @@
 
 (define_insn "movsidf2_low_rv32"
   [(set (match_operand:SI      0 "register_operand" "=  r")
-	(truncate:SI
-	    (match_operand:DF 1 "register_operand"  "zmvf")))]
+	(unspec:SI
+	    [(match_operand:DF 1 "register_operand" "zmvf")]
+	UNSPEC_FMV_X_W))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "fmove")
@@ -2636,11 +2639,10 @@
 
 
 (define_insn "movsidf2_high_rv32"
-  [(set (match_operand:SI      0 "register_operand"    "=  r")
-	(truncate:SI
-            (lshiftrt:DF
-                (match_operand:DF 1 "register_operand" "zmvf")
-                (const_int 32))))]
+  [(set (match_operand:SI      0 "register_operand" "=  r")
+	(unspec:SI
+	    [(match_operand:DF 1 "register_operand" "zmvf")]
+	UNSPEC_FMVH_X_D))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvh.x.d\t%0,%1"
   [(set_attr "move_type" "fmove")
-- 
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