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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-15 09:50:46 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-15 09:50:46 +0000 |
| commit | 28f636a0b0bfd52daaf177dab38b76c1fdde534c (patch) | |
| tree | 4d17030086a1077eaae86cd57eb014dba449054d /gcc/config/aarch64/atomics.md | |
| parent | 0431e8ae5bdb854bda5f9005e41c8c4d03f6d74e (diff) | |
| download | gcc-28f636a0b0bfd52daaf177dab38b76c1fdde534c.zip gcc-28f636a0b0bfd52daaf177dab38b76c1fdde534c.tar.gz gcc-28f636a0b0bfd52daaf177dab38b76c1fdde534c.tar.bz2 | |
aarch64: Add support for widening LDAPR instructions
gcc/ChangeLog:
* config/aarch64/atomics.md
(*aarch64_atomic_load<ALLX:mode>_rcpc_zext): New pattern.
(*aarch64_atomic_load<ALLX:mode>_rcpc_sext): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldapr-ext.c: New test.
Diffstat (limited to 'gcc/config/aarch64/atomics.md')
| -rw-r--r-- | gcc/config/aarch64/atomics.md | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index dc5f52e..9670bef 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -704,6 +704,28 @@ } ) +(define_insn "*aarch64_atomic_load<ALLX:mode>_rcpc_zext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (zero_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldapr<ALLX:atomic_sfx>\t%<GPI:w>0, %1" +) + +(define_insn "*aarch64_atomic_load<ALLX:mode>_rcpc_sext" + [(set (match_operand:GPI 0 "register_operand" "=r") + (sign_extend:GPI + (unspec_volatile:ALLX + [(match_operand:ALLX 1 "aarch64_sync_memory_operand" "Q") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_LDAP)))] + "TARGET_RCPC" + "ldaprs<ALLX:atomic_sfx>\t%<GPI:w>0, %1" +) + (define_insn "atomic_store<mode>" [(set (match_operand:ALLI 0 "aarch64_rcpc_memory_operand" "=Q,Ust") (unspec_volatile:ALLI |