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2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili5-313/+72
APX spec removed KEYLOCKER and SHA promotions from EVEX MAP4. https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html gas/ChangeLog: * NEWS: Mention that remove KEYLOCKER and SHA promotions from EVEX * MAP4. * config/tc-i386.c (process_operands): Removed special handling of * KEYLOCKER and SHA. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l: Removed KEYLOCKER * and SHA instructions. * testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-prefix.h: Removed KEYLOCKER and SHA instructions. * i386-dis-evex.h: Ditto. * i386-opc.tbl: Ditto. * i386-dis.c (print_vector_reg): Removed special handling of KEYLOCKER * and SHA.
2024-03-28x86: templatize RAO-INT insnsJan Beulich1-8/+4
It's only four of them, but still better to reduce redundancy.
2024-03-28x86: templatize ADX insnsJan Beulich1-6/+5
It's only two of them, but still better to reduce redundancy.
2024-03-28x86: templatize shift-double insnsJan Beulich2-331/+303
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the shift-double ones. While there also drop the APX form with ShiftCount omitted. Other shift and rotate insns were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either.
2024-03-28x86: templatize shift/rotate insnsJan Beulich2-264/+379
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with the "ordinary" shift and rotate ones. While there also drop the APX form of RCL/RCR with Imm1 omitted. Other shift insns as well as ROR/ROL were deliberately left without this form as well. Note that there's also no testsuite adjustment needed for this, indicating that the form wasn't tested either. Furthermore since RCL/RCR already had non-NDD APX forms, those end up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize binary ALU insnsJan Beulich2-449/+473
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a the more complex binary (two source) cases. Note how this adds a missing CheckOperandSize to one of the APX sub forms. Furthermore since SBB already had a non-NDD APX form, one ends up being added for the other 6 mnemonics, too.
2024-03-28x86: templatize unary ALU insnsJan Beulich2-16/+22
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Continue with a few simple unary (single source) cases.
2024-03-28x86: templatize INC/DECJan Beulich3-68/+80
With the multitude of new APX templates, it finally becomes desirable to further remove redundancy by also templatizing basic arithmetic insns. Start with the simplest case, accompanied by a necessary adjustment to i386-gen (such that template uses can also be at the start of a line). While there also drop a bogus (meaningless / unreachable) "break" as well as a unused variable (which I'm surprised compilers didn't warn about).
2024-03-19gas, aarch64: Add faminmax extensionSaurabh Jha4-2486/+2626
2024-03-18Regenerate AArch64 opcodes filesNick Clifton3-468/+583
2024-03-18aarch64: Add support for SVE ADDPT, SUBPT, MADPT, MLAPT instructionsYury Khrustalev1-0/+18
The following instructions are added in this patch: - ADDPT (predicated): Add checked pointer vectors (predicated). - ADDPT (unpredicated): Add checked pointer vectors (unpredicated). - SUBPT (predicated): Subtract checked pointer vectors (predicated). - SUBPT (unpredicated): Subtract checked pointer vectors (unpredicated). - MADPT: Multiply-add checked pointer vectors, writing multiplicand - MLAPT: Multiply-add checked pointer vectors, writing addend These instructions are part of Checked Pointer Arithmetic extension and are enabled when both CPA and SVE are enabled. To achieve this, both flag "+sve" and "+cpa" should be active. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18aarch64: Add support for (M)ADDPT and (M)SUBPT instructionsYury Khrustalev6-1/+78
The following instructions are added in this patch: - ADDPT and SUBPT - Add/Subtract checked pointer - MADDPT and MSUBPT - Multiply Add/Subtract checked pointer These instructions are part of Checked Pointer Arithmetic extension. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. A new flag "+cpa" added to documentation. This flag enables CPA extension. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
2024-03-18Arm64: check matching operands for predicated B16B16 insnsJan Beulich2-17/+17
Except for bfml{a,s} their 1st and 3rd operands need to match - pass the TIED macro argument accordingly. While doing that also slightly re-arrange table entries, such that all predicated insns are close together. At the same time change the existing test source to actually use non- matching operands for the respective bfml{a,s} forms.
2024-03-18Arm64: correct B16B16 indexed bf{mla,mls,mul}Jan Beulich1-3/+3
Their index is in bits 19, 20, and 22. Bit 11 in particular is already set in the base opcode. Note also how disassembler output didn't match assembler input in the respective testcase.
2024-03-15x86/APX: legacy promoted insns can't access %xmm16-%xmm31Jan Beulich1-0/+5
Irrespective of the encoding being EVEX, the usable SIMD register range continues to be limited to %xmm0-%xmm15. Enforce this in gas (but continue to generate code, as in principle we know how to encode things) and recognize/flag the case in the disassembler. Oddly enough wrong forms were actually used in the testsuite (register- only forms are then really meaningless to test here, and are hence dropped instead of adjusted). Convert the POP2 test that needs touching anyway (due to a bad ModR/M byte having been chosen) to .insn.
2024-03-13opcodes: Fix build verbosityChristophe Lyon2-8/+8
Add $(AM_V_xxx) in a few places where they were missing.
2024-03-08RISC-V: Support Zabha extension.Jiawei1-0/+74
The Zabha extension[1] supports for byte and halfword atomic memory operations. This patch add all instructions include in Zabha. Further work is waiting Zacas[2] merge. [1] https://github.com/riscv/riscv-zabha/tags [2] https://sourceware.org/pipermail/binutils/2023-May/127700.html Version log: Add new imply relation that Zabha extension implies A extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_implicit_subsets): New imply. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * testsuite/gas/riscv/zabha-32.d: New test. * testsuite/gas/riscv/zabha.d: New test. * testsuite/gas/riscv/zabha.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_AMOADD_B): New opcodes. (MASK_AMOADD_B): Ditto. (MATCH_AMOXOR_B): Ditto. (MASK_AMOXOR_B): Ditto. (MATCH_AMOOR_B): Ditto. (MASK_AMOOR_B): Ditto. (MATCH_AMOAND_B): Ditto. (MASK_AMOAND_B): Ditto. (MATCH_AMOMIN_B): Ditto. (MASK_AMOMIN_B): Ditto. (MATCH_AMOMAX_B): Ditto. (MASK_AMOMAX_B): Ditto. (MATCH_AMOMINU_B): Ditto. (MASK_AMOMINU_B): Ditto. (MATCH_AMOMAXU_B): Ditto. (MASK_AMOMAXU_B): Ditto. (MATCH_AMOSWAP_B): Ditto. (MASK_AMOSWAP_B): Ditto. (MATCH_AMOADD_H): Ditto. (MASK_AMOADD_H): Ditto. (MATCH_AMOXOR_H): Ditto. (MASK_AMOXOR_H): Ditto. (MATCH_AMOOR_H): Ditto. (MASK_AMOOR_H): Ditto. (MATCH_AMOAND_H): Ditto. (MASK_AMOAND_H): Ditto. (MATCH_AMOMIN_H): Ditto. (MASK_AMOMIN_H): Ditto. (MATCH_AMOMAX_H): Ditto. (MASK_AMOMAX_H): Ditto. (MATCH_AMOMINU_H): Ditto. (MASK_AMOMINU_H): Ditto. (MATCH_AMOMAXU_H): Ditto. (MASK_AMOMAXU_H): Ditto. (MATCH_AMOSWAP_H): Ditto. (MASK_AMOSWAP_H): Ditto. (DECLARE_INSN): New declare. * opcode/riscv.h (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-opc.c: New instructions.
2024-03-01s390: Print base register 0 as "0" in disassemblyJens Remus1-4/+13
Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Warn when register name type does not match operandJens Remus1-31/+31
Print a warning message when the register type of a specified register name does not match with the operand's register type: operand {#}: expected {access|control|floating-point|general|vector} register name [as {base|index} register] Introduce a s390-specific assembler option "warn-regtype-mismatch" with the values "strict", "relaxed", and "no" as well as an option "no-warn-regtype-mismatch" which control whether the assembler performs register name type checks and generates above warning messages. warn-regtype-mismatch=strict: Perform strict register name type checks. warn-regtype-mismatch=relaxed: Perform relaxed register name type checks, which allow floating-point register (FPR) names %f0 to %f15 to be specified as argument to vector register (VR) operands and vector register (VR) names %v0 to %v15 to be specified as argument to floating-point register (FPR) operands. This is acceptable as the FPRs are embedded into the lower halves of the VRs. Make "relaxed" the default, as GCC generates assembler code using FPR and VR interchangeably, which would cause assembler warnings to be generated with "strict". warn-regtype-mismatch=no: no-warn-regtype-mismatch: Disable any register name type checks. Tag .insn pseudo mnemonics as such, to skip register name type checks on those. They need to be skipped, as there do not exist .insn pseudo mnemonics for every possible operand register type combination. Keep track of the currently parsed operand number to provide it as reference in warning messages. To verify that the introduction of this change does not unnecessarily affect the compilation of existing code the GNU Binutils, GNU C Library, and Linux Kernel have been build with the new assembler, verifying that the assembler did not generate any of the new warning messages. gas/ * config/tc-s390.c: Handle new assembler options "[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate parsed register expressions with register type. Keep track of operand number being parsed. Print warning message in case of register type mismatch between instruction operand and parsed register expression. * doc/as.texi: Document new s390-specific assembler options "[no-]warn-regtype-mismatch[=strict|relaxed|no]". * NEWS: Mention new s390-specific register name type checks and related assembler option "warn-regtype-mismatch=strict| relaxed|no". * testsuite/gas/s390/s390.exp: Add test cases for new assembler option "warn-regtype-mismatch={strict|relaxed}". * testsuite/gas/s390/esa-g5.s: Fix register types in tests for didbr, diebr, tbdr, and tbedr. * testsuite/gas/s390/zarch-z13.s: Fix register types in tests for vgef, vgeg, vscef, and vsceg. * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s: Tests for assembler option "warn-regtype-mismatch=strict". * testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l: Likewise. * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s: Tests for assembler option "warn-regtype-mismatch=relaxed". * gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l: Likewise. * gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update test cases for assembler option "warn-regtype-mismatch" defaulting to "relaxed". * testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise. include/ * opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add instruction flag to tag .insn pseudo-mnemonics. opcodes/ * s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as such. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Add test cases for base/index register 0Jens Remus1-2/+3
While at it add comments to logic to omit base and/or index register 0 in s390 disassembly. opcodes/ * s390-dis.c: Add comments related to omitting base and/or index register 0 in disassembly. gas/ * testsuite/gas/s390/s390.exp: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.s: Add test cases for base and/or index register 0. * testsuite/gas/s390/zarch-base-index-0.d: Likewise. * testsuite/gas/s390/zarch-base-index-0-err.s: Add error test cases for base and/or index register 0. Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-03-01s390: Use proper string lengths when parsing opcode table flagsJens Remus1-3/+3
opcodes/ * s390-mkopc.c: Use proper string lengths when parsing opcode table flags. Fixes: c5306fed7d4 ("s390: Support for jump visualization in disassembly") Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2024-03-01s390: Whitespace fixes in conditional branch flavor descriptionsJens Remus1-3/+3
opcodes/ * s390-mkopc.c: Whitespace fixes in conditional branch flavor descriptions. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2024-03-01x86/APX: optimize certain XOR and SUB formsJan Beulich2-4/+4
While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately.
2024-02-29aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.Srinath Parvathaneni1-2/+2
The assembler wrongly expects plain register name instead of memory-form 2nd operand for gcsstr and gcssttr instructions. This patch fixes the issue.
2024-02-29PR21739, Inconsistent diagnosticsAlan Modra1-0/+2
PR 21739 cpu/ * mep.opc (parse_lo16, parse_unsigned7): Mark %function message as no-c-format. opcodes/ * mep-asm.c: Regenerate.
2024-02-29RISC-V: Add assembly support for TLSDESC.Tatsuyuki Ishi1-0/+1
gas/ * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype renamed to percent_op_relax_only as this matcher is extended to handle jalr as well which is not R-type. (riscv_ip): Apply the percent_op_relax_only rename and update comment. (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to TLS relocation check list. * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation generation. opcodes/ * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with %tlsdesc_call annotations.
2024-02-27aarch64: rename internals related to PAuth feature to use pauth in their ↵Matthieu Longo1-38/+38
naming for coherency Hi, Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion. Regression tested on aarch64-none-elf, and no regression found. Ok for binutils-master? I don't have commit access so I need someone to commit on my behalf. Regards, Matthieu. From 58b38358b2788939d81f2df7f5fb4c64a31ae06e Mon Sep 17 00:00:00 2001 From: Matthieu Longo <matthieu.longo@arm.com> Date: Fri, 23 Feb 2024 11:30:40 +0000 Subject: [PATCH] aarch64: rename internals related to PAuth feature to use pauth in their naming for coherency Commits af1bd77 and 3f4ff08 introduced the Pointer Authentication feature with internal names that don't match the actual feature name pauth. The new feature PAuth_LR introduced in Armv9.5-A is an extension of the PAuth feature of Armv8.3-A. Using a different naming for it not based on the formerly "PAC" would create confusion.
2024-02-23x86: also permit YMM/ZMM use in CFI directivesJan Beulich2-128/+129
Next to code using %ymm<N> or %zmm<N> it is more natural to have .cfi_* directives also reference those, not the corresponding %xmm<N>. Accept their names as kind of aliases, i.e. resolving to the same numbers. While extending the respective 64-bit testcase, also add %bnd<N> there (should have happened right with 633789901c83 ["x86-64: Dwarf2 register numbers for %bnd<N>"], sorry), requiring binutils/dwarf.c to be adjusted accordingly as well.
2024-02-23x86/APX: INV{EPT,PCID,VPID} are WIGJan Beulich2-6/+6
While various other entries in version 003 of the spec aren't quite as explicit (due to simply leaving the respective field blank), all three have a clear IGNORED there. IOW they ought to be emitted with EVEX.W=0 by default (and respect -mevexwig=).
2024-02-20kvx: gas: missing aliases for $r14r15 in assembler.Paul Iannetta1-10653/+10659
Most registers from a register-pair suffixed by .lo and .hi suffixes. This was not the case of $r14 and $r15 since they are defined by the ABI: $r14 is the frame pointer, and $r15 is used to return aggregates from functions. We do not add aliases for $r12 (the stack pointer) and $r13 (the tls register). opcodes/ChangeLog: * kvx-opc.c: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: enable magic immediates for integer multiply-accumulate and CMOVE*Paul Iannetta1-39/+1490
Affected instructions: - alu unit: cmovewp cmovehq - mau unit: maddwdp madduwdp maddsuwdp mma msbfwdp msbfuwdp msbfsuwdp mms mulwdp muluwdp mulsuwdp mm opcodes/ChangeLog: * kvx-opc.c (struct kvxopc): Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate.
2024-02-20kvx: gas: rename: or -> ior, xor -> eorPaul Iannetta1-2396/+5257
TCA instructions start with an X, this introduces ambiguities when it comes to XOR (Is it the OR on the TCA or the XOR of the core?). For this reason, we rename OR to IOR and XOR to EOR. OR and XOR variants are still valid on KV3-1 and KV3-2. However, they have been completely removed from KV4-1. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-20kvx: gas: move the splat modifier to the immediatePaul Iannetta1-1083/+1134
The position of the splat modifier is now after the operand it modifies and not attached directly to the opcode. opcodes/ChangeLog: * kvx-opc.c: Regenerate. include/ChangeLog: * opcode/kvx.h: Regenerate. gas/ChangeLog: * config/kvx-parse.h: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-1-insns-64.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-32.s: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.d: Regenerate. * testsuite/gas/kvx/kv3-2-insns-64.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-32.s: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.d: Regenerate. * testsuite/gas/kvx/kv4-1-insns-64.s: Regenerate.
2024-02-19aarch64: Add support for the id_aa64isar3_el1 system registerYury Khrustalev1-0/+1
Hi, [PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register AArch64 defines a read-only system register called id_aa64isar3_el1. This patch also adds relevant tests. Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets and no regressions was found. Is this Ok for trunk? I do not have commit rights, if OK, can someone commit on my behalf? Thanks, Yury Khrustalev From e42c835e8f2ee81150f498675f2faf108bbe79f8 Mon Sep 17 00:00:00 2001 From: Yury Khrustalev <yury.khrustalev@arm.com> Date: Tue, 6 Feb 2024 11:05:39 +0000 Subject: [PATCH] [PATCH][Binutils] aarch64: Add support for the id_aa64isar3_el1 system register AArch64 defines a read-only system register called id_aa64isar3_el1. This patch also adds relevant tests. Regression tested on the aarch64-none-elf and aarch64-none-linux-gnu targets and no regressions was found.
2024-02-16x86/APX: drop stray IgnoreSizeJan Beulich2-22/+22
While necessary on the legacy encodings, the EVEX ones don't need it. Even more so when they're available for 64-bit mode only, when the legacy encodings have the attribute only for correctly handling things in 16-bit mode.
2024-02-16x86: don't use VexWIG in SSE2AVX templatesJan Beulich2-8/+8
Several years ago it was decided that SSE2AVX templates should not be sensitive to -mvexwig= (upon my suggestion to consistently make all sensitive as long as they don't require a specific setting of VEX.W). Adjust the four that still are, switching to use of Vex128 at the same time.
2024-02-16x86: drop redundant XmmwordJan Beulich1-8/+8
While e20298da05f2 ("Remove redundant Byte, Word, Dword and Qword from insn templates") did so for Byte/Word/Dword/Qword, the same kind of redundancy was left in place for a few 128-bit SIMD operands.
2024-02-15objdump, as: add callx support for BPF CPU v1Will Hawkins2-1/+5
Albeit not being a currently valid BPF instruction, callx is generated by both clang and GCC when BPF programs are compiled unoptimized. Until now, GCC would emit it only whe using the experimental compiler-testing cpu version xbpf, whereas clang would emit it from v1. This patch makes GAS to accept callx also starting with cpu v1. opcodes/ChangeLog * bpf-opc.c: Move callx into the v1 BPF CPU variant. gas/ChangeLog * testsuite/gas/bpf/indcall-1-pseudoc.d: Do not select xbpf cpu version. * testsuite/gas/bpf/indcall-1.d: Likewise.
2024-02-14arc: Put DBNZ instruction to a separate classYuriy Kolerov3-1/+7
DBNZ instruction decrements its source register operand, and if the result is non-zero it branches to the location defined by a signed half-word displacement operand. DBNZ instruction is in BRANCH class as other branch instrucitons like B, Bcc, etc. However, DBNZ is the only branch instruction that stores a branch offset in the second operand. Thus it must be placed in a distinct class and treated differently. For example, current logic of arc_insn_get_branch_target in GDB assumes that a branch offset is always stored in the first operand for BRANCH class and it's wrong for DBNZ. include/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * opcode/arc.h (enum insn_class_t): Add DBNZ class. opcodes/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * arc-tbl.h (dbnz): Use "DBNZ" class. * arc-dis.c (arc_opcode_to_insn_type): Handle "DBNZ" class. gas/ChangeLog: 2024-02-14 Yuriy Kolerov <ykolerov@synopsys.com> * config/tc-arc.c (is_br_jmp_insn_p): Add check against "DBNZ".
2024-02-09PowerPC: Add support for Power11 optionsPeter Bergner1-1/+11
binutils/ * doc/binutils.texi (PowerPC -M option): Mention power11 and pwr11. gas/ * config/tc-ppc.c: (md_show_usage): Mention -mpower11 and -mpwr11. * doc/c-ppc.texi: Likewise. opcodes/ * ppc-dis.c (ppc_opts): Add "power11" and "pwr11" entries. (powerpc_init_dialect): Default to "power11".
2024-02-09x86/APX: with REX2 map 1 doesn't "chain" to maps 2 or 3Jan Beulich1-7/+5
Don't wander into three_byte_table[] when REX2 is present. While there also eliminate related confusion when accessing dis386_twobyte[]: There's nothing 3-byte-ish involved there. Dropping the odd variable gets things better in sync with 1-byte handling as well.
2024-02-09x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressedJan Beulich2-201/+285
Interestingly unlike VROUND{P,S}{S,D} and VPERM{F,I}128 they weren't even present in the x86-64-apx-egpr-inval testcase, hence why I overlooked that these can actually be encoded, (again) using suitable AVX512 counterparts. While there also "modernize" the adjacent AVX/AVX2 entries.
2024-02-09x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}Jan Beulich2-6/+6
In eea4357967b6 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I failed to add the AVX512* ISA dependency of the two new entries.
2024-02-09x86: change type of Dwarf2 register numbers in register tableJan Beulich1-2/+2
Already the %bnd<N> registers used numbers beyond 127, and eGPR ones are all out of reach for "signed char", at least when CHAR_BITS=8. Switch to "unsigned char", covering appropriately in places where the value returned for "none" actually matters (in tc_x86_parse_to_dw2regnum() this is actually achieved by altering how X_op is set).
2024-01-29bpf: there is no ldinddw nor ldabsdw instructionsJose E. Marchesi2-4/+5
There are no legacy ldind nor ldabs BPF instructions with BPF_SIZE_DW. For some reason we were (incorrectly) supporting these. This patch updates the opcodes so the instructions get removed and modifies the GAS manual and testsuite accordingly. See discussion at https://lore.kernel.org/bpf/110aad7a-f8a3-46ed-9fda-2f8ee54dcb89@linux.dev Tested in bpf-uknonwn-none target, x86-64-linux-gnu host. include/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * opcode/bpf.h (enum bpf_insn_id): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. opcodes/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * bpf-opc.c (bpf_opcodes): Remove BPF_INSN_LDINDDW and BPF_INSN_LDABSDW instructions. gas/ChangeLog: 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com> * doc/c-bpf.texi (BPF Instructions): There is no indirect 64-bit load instruction. (BPF Instructions): There is no absolute 64-bit load instruction. * testsuite/gas/bpf/mem.s: Update test accordingly. * testsuite/gas/bpf/mem-be-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-be.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.d: Likewise. * testsuite/gas/bpf/mem-pseudoc.s: Likewise. * testsuite/gas/bpf/mem.d: Likewise. * testsuite/gas/bpf/mem.s: Likewise.
2024-01-26aarch64: move SHA512 instructions to +sha3Andrew Carlotti1-5/+5
SHA512 instructions were added to the architecture at the same time as SHA3 instructions, but later than the SHA1 and SHA256 instructions. Furthermore, implementations must support either both or neither of the SHA512 and SHA3 instruction sets. However, SHA512 instructions were originally (and incorrectly) added to Binutils under the +sha2 flag. This patch moves SHA512 instructions under the +sha3 flag, which matches the architecture constraints and existing GCC and LLVM behaviour.
2024-01-26x86/APX: TILE{RELEASE,ZERO} have no EVEX encodingsJan Beulich2-2/+11
Re-using the entire VEX decode hierarchy for the respective major opcode has led to those two also being decoded as-if valid. Follow the earlier USE_X86_64_EVEX_{PFX,W}_TABLE approach to avoid this happening.
2024-01-26x86/APX: no need to have decode go through x86_64_table[]Jan Beulich3-76/+27
As suggested during review already, all such entries have their first slot as Bad_Opcode, so by adding two more enumerators we can avoid doing that decode step altogether.
2024-01-26x86/APX: optimize MOVBEJan Beulich2-36/+38
With identical source and destination it can be covered by the NDD-to- legacy conversion logic as well, even if in this case the original insn doesn't use an NDD encoding. The size savings are even better here, for the replacement (BSWAP) not having a ModR/M byte.
2024-01-26LoongArch: gas: Add support for s9 registermengqinggang1-0/+9
In LoongArch ABI, r22 register can be used as frame pointer or static register(s9). Link: https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc#general-purpose-registers
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