s390: Warn when register name type does not match operand

Print a warning message when the register type of a specified register
name does not match with the operand's register type:

operand {#}: expected {access|control|floating-point|general|vector}
  register name [as {base|index} register]

Introduce a s390-specific assembler option "warn-regtype-mismatch"
with the values "strict", "relaxed", and "no" as well as an option
"no-warn-regtype-mismatch" which control whether the assembler
performs register name type checks and generates above warning messages.

warn-regtype-mismatch=strict:
  Perform strict register name type checks.

warn-regtype-mismatch=relaxed:
  Perform relaxed register name type checks, which allow floating-point
  register (FPR) names %f0 to %f15 to be specified as argument to vector
  register (VR) operands and vector register (VR) names %v0 to %v15 to
  be specified as argument to floating-point register (FPR) operands.
  This is acceptable as the FPRs are embedded into the lower halves of
  the VRs. Make "relaxed" the default, as GCC generates assembler code
  using FPR and VR interchangeably, which would cause assembler warnings
  to be generated with "strict".

warn-regtype-mismatch=no:
no-warn-regtype-mismatch:
  Disable any register name type checks.

Tag .insn pseudo mnemonics as such, to skip register name type checks
on those. They need to be skipped, as there do not exist .insn pseudo
mnemonics for every possible operand register type combination. Keep
track of the currently parsed operand number to provide it as reference
in warning messages.

To verify that the introduction of this change does not unnecessarily
affect the compilation of existing code the GNU Binutils, GNU C Library,
and Linux Kernel have been build with the new assembler, verifying that
the assembler did not generate any of the new warning messages.

gas/
	* config/tc-s390.c: Handle new assembler options
	"[no]warn-regtype-mismatch[=strict|relaxed|no". Annotate
	parsed register expressions with register type. Keep track of
	operand number being parsed. Print warning message in case of
	register type mismatch between instruction operand and parsed
	register expression.
	* doc/as.texi: Document new s390-specific assembler options
	"[no-]warn-regtype-mismatch[=strict|relaxed|no]".
	* NEWS: Mention new s390-specific register name type checks and
	related assembler option "warn-regtype-mismatch=strict|
	relaxed|no".
	* testsuite/gas/s390/s390.exp: Add test cases for new assembler
	option "warn-regtype-mismatch={strict|relaxed}".
	* testsuite/gas/s390/esa-g5.s: Fix register types in tests for
	didbr, diebr, tbdr, and tbedr.
	* testsuite/gas/s390/zarch-z13.s: Fix register types in tests
	for vgef, vgeg, vscef, and vsceg.
	* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.s:
	Tests for assembler option "warn-regtype-mismatch=strict".
	* testsuite/gas/s390/zarch-warn-regtype-mismatch-strict.l:
	Likewise.
	* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.s:
	Tests for assembler option "warn-regtype-mismatch=relaxed".
	* gas/testsuite/gas/s390/zarch-warn-regtype-mismatch-relaxed.l:
	Likewise.
	* gas/testsuite/gas/s390/zarch-omitted-base-index-err.s: Update
	test cases for assembler option "warn-regtype-mismatch"
	defaulting to "relaxed".
	* testsuite/gas/s390/zarch-omitted-base-index-err.l: Likewise.

include/
	* opcode/s390.h (S390_INSTR_FLAG_PSEUDO_MNEMONIC): Add
	instruction flag to tag .insn pseudo-mnemonics.

opcodes/
	* s390-opc.c (s390_opformats): Tag .insn pseudo-mnemonics as
	such.

Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>

1 files changed, 31 insertions, 31 deletions

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 377a4a9..10482fb 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -774,37 +774,37 @@ unused_s390_operands_static_asserts (void)
 
 const struct s390_opcode s390_opformats[] =
   {
-  { "e",    OP8(0x00LL), MASK_E,	   INSTR_E,	      3,  0, 0, NULL },
-  { "ri",   OP8(0x00LL), MASK_RI_RI,	   INSTR_RI_RI,	      3,  0, 0, NULL },
-  { "rie",  OP8(0x00LL), MASK_RIE_RRP,	   INSTR_RIE_RRP,     3,  0, 0, NULL },
-  { "ril",  OP8(0x00LL), MASK_RIL_RP,	   INSTR_RIL_RP,      3,  0, 0, NULL },
-  { "rilu", OP8(0x00LL), MASK_RIL_RU,	   INSTR_RIL_RU,      3,  0, 0, NULL },
-  { "ris",  OP8(0x00LL), MASK_RIS_RURDI,   INSTR_RIS_RURDI,   3,  6, 0, NULL },
-  { "rr",   OP8(0x00LL), MASK_RR_RR,	   INSTR_RR_RR,       3,  0, 0, NULL },
-  { "rre",  OP8(0x00LL), MASK_RRE_RR,	   INSTR_RRE_RR,      3,  0, 0, NULL },
-  { "rrf",  OP8(0x00LL), MASK_RRF_RURR,	   INSTR_RRF_RURR,    3,  0, 0, NULL },
-  { "rrs",  OP8(0x00LL), MASK_RRS_RRRDU,   INSTR_RRS_RRRDU,   3,  6, 0, NULL },
-  { "rs",   OP8(0x00LL), MASK_RS_RRRD,	   INSTR_RS_RRRD,     3,  0, 0, NULL },
-  { "rse",  OP8(0x00LL), MASK_RSE_RRRD,	   INSTR_RSE_RRRD,    3,  0, 0, NULL },
-  { "rsi",  OP8(0x00LL), MASK_RSI_RRP,	   INSTR_RSI_RRP,     3,  0, 0, NULL },
-  { "rsy",  OP8(0x00LL), MASK_RSY_RRRD,	   INSTR_RSY_RRRD,    3,  3, 0, NULL },
-  { "rx",   OP8(0x00LL), MASK_RX_RRRD,	   INSTR_RX_RRRD,     3,  0, 0, NULL },
-  { "rxe",  OP8(0x00LL), MASK_RXE_RRRD,	   INSTR_RXE_RRRD,    3,  0, 0, NULL },
-  { "rxf",  OP8(0x00LL), MASK_RXF_RRRDR,   INSTR_RXF_RRRDR,   3,  0, 0, NULL },
-  { "rxy",  OP8(0x00LL), MASK_RXY_RRRD,	   INSTR_RXY_RRRD,    3,  3, 0, NULL },
-  { "s",    OP8(0x00LL), MASK_S_RD,	   INSTR_S_RD,	      3,  0, 0, NULL },
-  { "si",   OP8(0x00LL), MASK_SI_URD,	   INSTR_SI_URD,      3,  0, 0, NULL },
-  { "siy",  OP8(0x00LL), MASK_SIY_URD,	   INSTR_SIY_URD,     3,  3, 0, NULL },
-  { "sil",  OP8(0x00LL), MASK_SIL_RDI,     INSTR_SIL_RDI,     3,  6, 0, NULL },
-  { "ss",   OP8(0x00LL), MASK_SS_RRRDRD,   INSTR_SS_RRRDRD,   3,  0, 0, NULL },
-  { "sse",  OP8(0x00LL), MASK_SSE_RDRD,	   INSTR_SSE_RDRD,    3,  0, 0, NULL },
-  { "ssf",  OP8(0x00LL), MASK_SSF_RRDRD,   INSTR_SSF_RRDRD,   3,  0, 0, NULL },
-  { "vrv",  OP8(0x00LL), MASK_VRV_VVXRDU,  INSTR_VRV_VVXRDU,  3,  9, 0, NULL },
-  { "vri",  OP8(0x00LL), MASK_VRI_VVUUU,   INSTR_VRI_VVUUU,   3,  9, 0, NULL },
-  { "vrx",  OP8(0x00LL), MASK_VRX_VRRDU,   INSTR_VRX_VRRDU,   3,  9, 0, NULL },
-  { "vrs",  OP8(0x00LL), MASK_VRS_RVRDU,   INSTR_VRS_RVRDU,   3,  9, 0, NULL },
-  { "vrr",  OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3,  9, 0, NULL },
-  { "vsi",  OP8(0x00LL), MASK_VSI_URDV,	   INSTR_VSI_URDV,    3, 10, 0, NULL },
+  { "e",    OP8(0x00LL), MASK_E,	   INSTR_E,	      3,  0, 256, NULL },
+  { "ri",   OP8(0x00LL), MASK_RI_RI,	   INSTR_RI_RI,	      3,  0, 256, NULL },
+  { "rie",  OP8(0x00LL), MASK_RIE_RRP,	   INSTR_RIE_RRP,     3,  0, 256, NULL },
+  { "ril",  OP8(0x00LL), MASK_RIL_RP,	   INSTR_RIL_RP,      3,  0, 256, NULL },
+  { "rilu", OP8(0x00LL), MASK_RIL_RU,	   INSTR_RIL_RU,      3,  0, 256, NULL },
+  { "ris",  OP8(0x00LL), MASK_RIS_RURDI,   INSTR_RIS_RURDI,   3,  6, 256, NULL },
+  { "rr",   OP8(0x00LL), MASK_RR_RR,	   INSTR_RR_RR,       3,  0, 256, NULL },
+  { "rre",  OP8(0x00LL), MASK_RRE_RR,	   INSTR_RRE_RR,      3,  0, 256, NULL },
+  { "rrf",  OP8(0x00LL), MASK_RRF_RURR,	   INSTR_RRF_RURR,    3,  0, 256, NULL },
+  { "rrs",  OP8(0x00LL), MASK_RRS_RRRDU,   INSTR_RRS_RRRDU,   3,  6, 256, NULL },
+  { "rs",   OP8(0x00LL), MASK_RS_RRRD,	   INSTR_RS_RRRD,     3,  0, 256, NULL },
+  { "rse",  OP8(0x00LL), MASK_RSE_RRRD,	   INSTR_RSE_RRRD,    3,  0, 256, NULL },
+  { "rsi",  OP8(0x00LL), MASK_RSI_RRP,	   INSTR_RSI_RRP,     3,  0, 256, NULL },
+  { "rsy",  OP8(0x00LL), MASK_RSY_RRRD,	   INSTR_RSY_RRRD,    3,  3, 256, NULL },
+  { "rx",   OP8(0x00LL), MASK_RX_RRRD,	   INSTR_RX_RRRD,     3,  0, 256, NULL },
+  { "rxe",  OP8(0x00LL), MASK_RXE_RRRD,	   INSTR_RXE_RRRD,    3,  0, 256, NULL },
+  { "rxf",  OP8(0x00LL), MASK_RXF_RRRDR,   INSTR_RXF_RRRDR,   3,  0, 256, NULL },
+  { "rxy",  OP8(0x00LL), MASK_RXY_RRRD,	   INSTR_RXY_RRRD,    3,  3, 256, NULL },
+  { "s",    OP8(0x00LL), MASK_S_RD,	   INSTR_S_RD,	      3,  0, 256, NULL },
+  { "si",   OP8(0x00LL), MASK_SI_URD,	   INSTR_SI_URD,      3,  0, 256, NULL },
+  { "siy",  OP8(0x00LL), MASK_SIY_URD,	   INSTR_SIY_URD,     3,  3, 256, NULL },
+  { "sil",  OP8(0x00LL), MASK_SIL_RDI,     INSTR_SIL_RDI,     3,  6, 256, NULL },
+  { "ss",   OP8(0x00LL), MASK_SS_RRRDRD,   INSTR_SS_RRRDRD,   3,  0, 256, NULL },
+  { "sse",  OP8(0x00LL), MASK_SSE_RDRD,	   INSTR_SSE_RDRD,    3,  0, 256, NULL },
+  { "ssf",  OP8(0x00LL), MASK_SSF_RRDRD,   INSTR_SSF_RRDRD,   3,  0, 256, NULL },
+  { "vrv",  OP8(0x00LL), MASK_VRV_VVXRDU,  INSTR_VRV_VVXRDU,  3,  9, 256, NULL },
+  { "vri",  OP8(0x00LL), MASK_VRI_VVUUU,   INSTR_VRI_VVUUU,   3,  9, 256, NULL },
+  { "vrx",  OP8(0x00LL), MASK_VRX_VRRDU,   INSTR_VRX_VRRDU,   3,  9, 256, NULL },
+  { "vrs",  OP8(0x00LL), MASK_VRS_RVRDU,   INSTR_VRS_RVRDU,   3,  9, 256, NULL },
+  { "vrr",  OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3,  9, 256, NULL },
+  { "vsi",  OP8(0x00LL), MASK_VSI_URDV,	   INSTR_VSI_URDV,    3, 10, 256, NULL },
 };
 
 const int s390_num_opformats =