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2025-12-09LoongArch: Add support for the ud macro instructionLulu Cai1-0/+1
In the "ud ui5" macro, the value of ui5 must be in the range 0–31. It expands to "amswap.w $rd, $r1, $rj", where ui5 specifies the register number for $rd in the amswap.w instruction, and $rd == $rj. The test case have been adjusted to no longer report errors for illegal operands of the amswap.w instruction. gas/ * config/tc-loongarch.c (check_this_insn_before_appending): No longer check amswap.w. * testsuite/gas/loongarch/illegal-operand.l: Update. * testsuite/gas/loongarch/illegal-operand.s: Update. * testsuite/gas/loongarch/macro_ud.d: New test. * testsuite/gas/loongarch/macro_ud.s: New test. include/ * opcode/loongarch.h: Add new macro for amswap.w. opcodes/ * loongarch-opc.c: Add macro for ud.
2025-12-08Fix typo in aarch64-opc.cNick Clifton1-1/+1
2025-12-05Add AMD znver6 processor supportUmesh Kalvakuntla10-3643/+3760
In --help option, adds znver6 to the list of CPUs under -march. Please find the ISA descriptions for AVX512_BMM instructions below. AVX512 Bit Manipulation Instructions ==================================== The AVX512BMM instructions include Bit Matrix Multiply and Bit Reversal operations. CPUID ----- Support is indicated by the new CPUID 8000_0021, EAX bit 23, labeled AVX512_BMM. Encoding -------- VBMACOR16x16x16 EVEX.256.NP.MAP6.W0 80 /r VBMACOR16x16x16 ymm1, ymm2, ymm3/m256 EVEX.512.NP.MAP6.W0 80 /r VBMACOR16x16x16 zmm1, zmm2, zmm3/m512 VBMACXOR16x16x16 EVEX.256.NP.MAP6.W1 80 /r VBMACXOR16x16x16 ymm1, ymm2, ymm3/m256 EVEX.512.NP.MAP6.W1 80 /r VBMACXOR16x16x16 zmm1, zmm2, zmm3/m512 DESCRIPTION ----------- 256 BIT VERSIONS ---------------- 16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR reduction. A ymm register holds a 16x16 bit matrix. The third source matrix for accumulation is in ymm1. 512 BIT VERSIONS ---------------- 2 parallel 16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR reduction. Each 256-bit chunk of a zmm register holds a 16x16 bit matrix. The third source matrices for accumulation are in zmm1. VBITREVB -------- EVEX.128.NP.MAP6.W0 81 /r VBITREVB xmm1{k1}{z}, xmm2/m128 EVEX.256.NP.MAP6.W0 81 /r VBITREVB ymm1{k1}{z}, ymm2/m256 EVEX.512.NP.MAP6.W0 81 /r VBITREVB zmm1{k1}{z}, zmm2/m512 DESCRIPTION ----------- Bit reversal within a byte boundary. Only applied to input bytes where the corresponding mask bit is set; otherwise, bytes are left untouched or zeroed out if zero masking is indicated. gas/ChangeLog: * NEWS: Add znver6 ARCH. * config/tc-i386.c: Add znver6 ARCH, avx512_bmm SUBARCH. * doc/c-i386.texi: Likewise. * testsuite/gas/i386/i386.exp: Add znver6 test cases. * testsuite/gas/i386/x86-64.exp: Add znver6 test cases. * testsuite/gas/i386/arch-16-znver6.d: New test. * testsuite/gas/i386/arch-16.d: New test. * testsuite/gas/i386/arch-16.s: New test. * testsuite/gas/i386/avx512_bmm.d: New test. * testsuite/gas/i386/avx512_bmm.s: New test. * testsuite/gas/i386/avx512_bmm_vl-inval.l: New test. * testsuite/gas/i386/avx512_bmm_vl-inval.s: New test. * testsuite/gas/i386/avx512_bmm_vl.d: New test. * testsuite/gas/i386/avx512_bmm_vl.s: New test. * testsuite/gas/i386/x86-64-arch-6-znver6.d: New test. * testsuite/gas/i386/x86-64-arch-6.d: New test. * testsuite/gas/i386/x86-64-arch-6.s: New test. * testsuite/gas/i386/x86-64-avx512_bmm-bad.d: New test. * testsuite/gas/i386/x86-64-avx512_bmm-bad.s: New test. * testsuite/gas/i386/x86-64-avx512_bmm.d: New test. * testsuite/gas/i386/x86-64-avx512_bmm.s: New test. * testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l: New test. * testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s: New test. * testsuite/gas/i386/x86-64-avx512_bmm_vl.d: New test. * testsuite/gas/i386/x86-64-avx512_bmm_vl.s: New test. opcodes/ChangeLog: * i386-dis-evex-len.h: Likewise. * i386-dis-evex-w.h: Likewise. * i386-dis-evex.h: Likewise. * i386-dis.c: Add EVEX_W_MAP6_80, EVEX_W_MAP6_81, EVEX_LEN_MAP6_80_W_0, EVEX_LEN_MAP6_80_W_1. * i386-gen.c: Likewise. * i386-init.h: Re-generated. * i386-mnem.h: Re-generated. * i386-opc.h (enum i386_cpu): Add CpuAVX512_BMM. (i386_cpu_flags): Add cpuvavx512_bmm. * i386-opc.tbl: Add vbmacor16x16x16, vbmacxor16x16x16, vbitrevb. * i386-tbl.h: Re-generated.
2025-12-05x86: sub-divide APX_F - NCI-NDD-NF and testingJan Beulich2-0/+13
To reflect spec version 007's introduction of the three-way APX-NCI-NDD-NF also introduce a respective ISA specifier, without that actually having a counterpart in opcodes. Add a testcase to cover all four new ISA specifiers.
2025-12-05x86: sub-divide APX_F - NFJan Beulich5-391/+419
While spec version 007 introduced the three-way APX-NCI-NDD-NF, let's split the three aspects (NCI, NDD, and NF) in gas. For NF we only need to guard the {nf} pseudo-prefix.
2025-12-05x86: sub-divide APX_F - NDDJan Beulich5-441/+758
While spec version 007 introduced the three-way APX-NCI-NDD-NF, let's split the three aspects (NCI, NDD, and NF) in gas. Note that NDD also applies to a number of EVEX-encoded insns with EVEX.ndd clear. Some extra logic is needed in cpu_flags_match() to avoid the need to add APX_NDD to CPU_FLAGS_COMMON.
2025-12-05x86: sub-divide APX_F - NCIJan Beulich5-446/+472
While spec version 007 introduced the three-way APX-NCI-NDD-NF, let's split the three aspects (NCI, NDD, and NF) in gas. While adjusting CMOVcc and CFCMOVcc, drop the bogus CpuCMOV dependencies. Such a requirement was never specified in any public doc revision. Note also that the EVEX-encoded forms of TEST were lacking CpuAPX_F so far.
2025-12-05x86: correct {RD,WR}{FS,GS}BASE {dis,}assemblyJan Beulich4-9/+39
First they are valid only in 64-bit mode. And then an operand size prefix has no meaning here, hence v_mode is wrong to use; switch to dq_mode.
2025-12-04aarch64: Enable `-M notes' by defaultAlice Carlotti1-2/+2
We already print other instruction comments, such as condition code aliases, by default. The `-M no-notes' option has been available in Binutils for over 7 years, so if anyone does need the notes to be disabled then they can do so explicitly.
2025-12-04aarch64: Refactor sysreg operand printingAlice Carlotti1-48/+54
This hopefully makes the logic clearer. It also adds NULL checks before recording notes, and explicitly compares the inexactness of inexact matches (although this extra comparison isn't used for any existing encodings).
2025-12-04aarch64: Fix incorrect sysreg notes operand notesAlice Carlotti1-2/+4
When support for Armv8-R was added in 2020, aarch64_print_operand was modified to check architecture features when searching for a system register name. However, this mismatch is then conflated with read-only/write-only mismatches, leading to incorrect note emission when reading a read-only or writing a write-only system register that is not available in whichever of Armv8-A or Armv8-R we are using. The original code also segfaults when parsing `msr mpuir_el1, w1'. This segfault arises while suggesting alternative assembler input with corrected qualifiers, due to a missing NULL check when attempting to emit notes. The segfault is unreachable after this change, but a subsequent patch will incorporate NULL checking anyway. Once notes are enabled by default, an existing `mrs x0, mpuir_el1' test will verify that the incorrect notes are no longer generated.
2025-11-28x86: drop a few excess AVX512VL from opcode tableJan Beulich2-13/+13
In commit 24187fb9c0d0 ("x86/APX: extend SSE2AVX coverage") I apparently went a little to far with AVX512VL uses: - PEXTRQ and PINSRQ are AVX512DQ alone, despite using 128-bit (XMM) registers, - SSE41DQ is used for only PEXTRD and PINSRD, falling in the same category. With the SSE41DQ observation above, also simplify Disp8MemShift handling there: No need to override it in the insn template, as long as the manufacturing template specifies it correctly. Note that the AVX512DW form of PINSRQ also had a stray "AVX" CPU specifier on it. Make this disappear by templatizing via a new SSE41DQ64 manufacturing template (covering PEXTRQ and PINSRQ, paralleling SSE41DQ).
2025-11-13PowerPC: Add support for RFC02660 - Context Switch InstructionAbhay Kandpal1-0/+1
opcodes/ * ppc-opc.c: (powerpc_opcodes): Add mtlpl. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-11-13PowerPC: Support for Controlled Cluster Memory (RFC02689)Abhay Kandpal1-0/+3
opcodes/ * ppc-opc.c (powerpc_opcodes): Add ccmclean, ccmrl. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-11-07x86: support SALCJan Beulich4-2079/+2090
Now that the SDM (finally) at least mentions it (without giving it a proper instruction page, though), let's (again: finally) also support it in assembler and disassembler.
2025-11-03tidy m4 plugin config supportAlan Modra1-65/+64
In CLANG_PLUGIN_FILE it is possible for plugin_file to be non-NULL when LLVMgold.so does not exist. configure output is messy, with results not printed against their "checking.." line, eg. checking for clang... (cached) yes checking for clang plugin file... checking for x86_64-pc-linux-gnu-ar... (cached) ar --plugin /usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so /usr/lib/llvm-20/lib/clang/20/../../LLVMgold.so This patch fixes those problems, and a similar interposition of other configure output between AC_MSG_CHECKING and AC_MSG_RESULT in gcc-plugin.m4. It also tidies some of the message text, and makes similar code in gcc-plugin.m4 and clang-plugin.m4 a little more consistent. config/ * clang-plugin.m4 (CLANG_PLUGIN_FILE): Don't place checks for tools (llvm-config, ar) inside AC_MSG_CHECKING..AC_MSG_RESULT for clang plugin file. Clear plugin_file before loop exit. (CLANG_PLUGIN_FILE_FOR_TARGET): Similarly. * gcc-plugin.m4 (GCC_PLUGIN_OPTION): Similarly. (GCC_PLUGIN_OPTION_FOR_TARGET): Correct AC_MSG_CHECKING. Tidy return code. binutils/ * testsuite/lib/binutils-common.exp <llvm_plug_opt>: Set for non-native. * configure: Regenerate. / * configure: Regenerate. bfd/ * configure: Regenerate. gas/ * configure: Regenerate. gdb/ * configure: Regenerate. gprof/ * configure: Regenerate. gprofng/ * configure: Regenerate. * libcollector/configure: Regenerate. ld/ * configure: Regenerate. libbacktrace/ * configure: Regenerate. libctf/ * configure: Regenerate. libiberty/ * configure: Regenerate. libsframe/ * configure: Regenerate. opcodes/ * configure: Regenerate. sim/ * configure: Regenerate. zlib/ * configure: Regenerate.
2025-10-30s390: Do not generate incomplete opcode tableJens Remus2-2/+4
The s390 opcode table s390-opc.tbl is generated from s390-opc.txt using the s390-mkopc utility using output redirection. If s390-mkopc fails with a non-zero return code, e.g. due to a warning or error, an incomplete opcode table may be generated in the build directory. A subsequent invocation of make then assumes that incomplete opcode table to be up to date. Depending on the s390-mkopc issue the build may then proceed without any follow-on warnings or errors, causing the preceding error or warning to go unnoticed. Generate the s390 opcode table into an intermediate temporary file s390-opc.tbl.tmp in the build directory and only move it to the final target s390-opc.tbl if the generation was successful. Tested by appending an unsupported inline comment "# TEST" to one of the instructions defined in s390-opc.txt. opcodes/ * Makefile.am (s390-opc.tab): Use an intermediate temporary file to prevent updating of the target on error/warning. * Makefile.in: Regenerated. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2025-10-29x86: Disable AMX-TRANSPOSE by defaultHaochen Jiang2-2/+2
In Binutils, we choose to keep the AMX-TRANSPOSE support for now in case there are vendors want to utilize the instructions although the feature itself is de-published. AMX-TRANSPOSE will not show up on any Intel/AMD hardware. Also in foreseeable future, no hardware will support AMX-TRANSPOSE, we will disable it by default. gas/ChangeLog: * testsuite/gas/i386/x86-64-amx-movrs-intel.d: Move AMX-TRANSPOSE part to AMX-TRANSPOSE test. * testsuite/gas/i386/x86-64-amx-movrs.d: Ditto. * testsuite/gas/i386/x86-64-amx-movrs.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-bad.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.d: Ditto. * testsuite/gas/i386/x86-64-amx-tf32.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-wig.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted.s: Ditto. * testsuite/gas/i386/x86-64-amx-movrs-inval.l: Move AMX-TRANSPOSE part to AMX-TRANSPOSE file. Remove noamx_transpose test. * testsuite/gas/i386/x86-64-amx-movrs-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-bad.d: Add AMX-MOVRS and AMX-TF32 related test. * testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto. * testsuite/gas/i386/x86-64.exp: Remove AMX-MOVRS invalid test. * testsuite/gas/i386/x86-64-amx-transpose-apx-intel.d: New test originally comes from APX_F test. * testsuite/gas/i386/x86-64-amx-transpose-apx-wig.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-apx.d: Ditto. * testsuite/gas/i386/x86-64-amx-transpose-apx.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Disable AMX-TRANSPOSE by default. * i386-init.h: Regenerated.
2025-10-29Revert "x86/APX: drop AMX-TRANSPOSE promoted insns"Haochen Jiang4-20/+34
This reverts commit bafcf0823c1ae4c2201670225c9cf14ccf2abc67. The patch (the removal) was done on the wrong assumption that it was only the APX-promoted forms which would be dropped because the APX spec was updated ahead of ISE and there was no info that AMX-TRANSPOSE would be de-published at that time. Given the current situation, since we will choose to disable AMX-TRANSPOSE but not to remove the support in Binutils, we will also not remove the APX support.
2025-10-28PowerPC: Support for Load/Store VSX Vector Paired Byte*32 Indexed (RFC02678)Abhay Kandpal1-0/+4
opcodes/ * ppc-opc.c (powerpc_opcodes): Add lxvpb32x, stxvpb32x. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2025-10-28aarch64: gas: Allow movprfx with fmmla and bfscale [PR gas/33562]Alfie Richards1-13/+13
These instructions were previously incorrectly marked as not accepting movprfx. Fix this and add tests. PR gas/33562 opcodes: * aarch64-tbl.h: Update widening fmmmla and bfscale instructions. gas: * testsuite/gas/aarch64/f8f16mm_sve2-bad.l: Update test with movprfx. * testsuite/gas/aarch64/f8f16mm_sve2.d: Ditto. * testsuite/gas/aarch64/f8f16mm_sve2.s: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2-bad.l: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2.d: Ditto. * testsuite/gas/aarch64/f8f32mm_sve2.s: Ditto. * testsuite/gas/aarch64/sve-f16f32mm-bad.l: Ditto. * testsuite/gas/aarch64/sve-f16f32mm.d: Ditto. * testsuite/gas/aarch64/sve-f16f32mm.s: Ditto. * testsuite/gas/aarch64/sve-bfscale-sve2.s: Ditto. * testsuite/gas/aarch64/sve-bfscale-sve2.d: Ditto. Approved-By: Alice Carlotti <alice.carlotti@arm.com>
2025-10-10x86: PadLock adjustmentsJan Beulich5-97/+101
For one, all PadLock insns depend on CR4.FXSR to be enabled, which means they ought to be taking FXSR as a prereq. Furthermore none of them permits a REPNE prefix; such forms are documented to cause #UD. (This is mainly relevant for XSTORE, which doesn't include a REP prefix in its base encoding. For the others this merely is a change in what diagnostic is issued.) Finally it is documented that an operand size prefix also causes #UD.
2025-10-10aarch64: Add support for FEAT_SSVE_BITPERMAlice Carlotti1-1/+1
2025-10-10aarch64: Add support for FEAT_SSVE_FEXPAAlice Carlotti1-1/+7
2025-10-10aarch64: Add support for FEAT_SME_MOP4Alice Carlotti7-187/+1923
2025-10-10aarch64: Add support for FEAT_SME_TMOPAlice Carlotti7-430/+654
2025-10-10aarch64: Remove incorrect disassembly constraintAlice Carlotti2-12/+0
A check in print_insn_aarch64_word asserted that part of the encoding space couldn't contain any valid encodings, and then returned ERR_NYI ("Not Yet Implemented", perhaps?) for these values. However, some of the new FEAT_MOP4 instructions will trigger the assert. The check seems to be outdated, and is clearly no longer valid, so it can just be deleted. Additionally, there are no other assignments of ERR_NYI, so delete all remaining references to this error type.
2025-10-10aarch64: Use constant fields in simple_index operandsAlice Carlotti6-80/+86
Update aarch64_{ins|ext}_simple_index to use constant fields, and swap the order of the index and regno fields, so that the regno occupies the last five bits. (Splitting/combining a variable length value and a fixed length value is easiest if the fixed length value occupies the least significant bits.)
2025-10-10aarch64: Allow multiple fields for sve_aligned_reglistAlice Carlotti6-20/+20
Update aarch64_{ins|ext}_sve_aligned_reglist to use constant fields instead of operand specific data for zero-extension/truncation.
2025-10-10aarch64: Allow multiple fields in {ins|ext}_regnoAlice Carlotti4-8/+7
Adjust SME_PNd3/SME_PNg3 to use explicit FLD_CONST_1 bits. This allows the use of operand specific data to be eliminated here.
2025-10-10aarch64: Extend aarch64_field to support constantsAlice Carlotti4-235/+272
Many instructions have constraints on the range of registers they can use. This means that some bits in the register number are fixed, and therefore aren't mapped to a field in the instruction encoding. Currently we use various adhoc rules to handle these fixed bits, but this doesn't handle all cases and we often have to write new code to support new combinations of permitted registers. This patch allows these constant bits to instead be specified in the same structure used to represent instruction fields. Uses of the new constant fields will be introduced in subsequent patches.
2025-10-06aarch64: GICv5 hypervisor control system registersMatthieu Longo1-0/+31
This patch adds support for hypervisor control registers on AArch64, available via the Generic Interrupt Controller v5 feature, and enabled via the +gcie flag. - ich_apr_el2 - ich_contextr_el2 - ich_hfgitr_el2 - ich_hfgrtr_el2 - ich_hfgwtr_el2 - ich_hppir_el2 (RO) - ich_ppi_activer[0,1]_el2 - ich_ppi_dvir[0,1]_el2 - ich_ppi_enabler[0,1]_el2 - ich_ppi_pendr[0,1]_el2 - ich_ppi_priorityr[0,15]_el2 - ich_vctlr_el2 - ich_vmcr_el2
2025-10-06aarch64: GICv5 PPI system registersMatthieu Longo1-0/+32
This patch adds support for PPI registers on AArch64, available via the Generic Interrupt Controller v5 feature, and enabled via the +gcie flag. - icc_ppi_cactiver[0,1]_el1 - icc_ppi_cpendr[0,1]_el1 - icc_ppi_enabler[0,1]_el1 - icc_ppi_hmr[0,1]_el1 (RO) - icc_ppi_priorityr[0,15]_el1 - icc_ppi_sactiver[0,1]_el1 - icc_ppi_spendr[0,1]_el1 Also, the new system register 'icc_ppi_priorityr8_el1' clashed with the encoding of 's3_0_c12_c15_0' used in a test for the generic syntax of system registers using mrs and msr. This patch replaces 's3_0_c12_c15_0' in the test by an unused encoding: s3_7_c0_c15_0.
2025-10-06aarch64: GICv5 CPU interface system registersMatthieu Longo1-0/+13
This patch adds support for 13 new AArch64 system registers for the CPU interface, which are enabled on using Generic Interrupt Controller v5 (+gcie flag) feature: - 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3 ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3. - 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1, ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1. Note: the already-existing ID_AA64PFR2_EL1 register is required by the GICv5 feature.
2025-10-06gas: aarch64: Add instructions for GICv5Saurabh Jha7-2/+89
Add new instructions from the Generic Interrupt Controller, GICv5, extension. These instructions are aliases to system instructions and are the following: * gic <operation>, <reg> * gicr <reg>, <operation> * gsb <operation>
2025-10-06gas: aarch64: Add flag for GICv5Saurabh Jha1-0/+3
Generic Interrupt Controller v5, GICv5, adds new system registers and system instructions. These are enabled with the +gcie flag, where gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt Extension.
2025-10-06msp430: extended_dst disassemblyAlan Modra1-11/+22
This avoids a gcc-14.2 bug reporting an "error: null destination pointer" on an sprintf buffer that is not NULL. Don't ask me why this happens to work. * msp430-dis.c (msp430_singleoperand): Don't overprint op or comm for extended_dst.
2025-10-04opcodes: PR 33384 invalid disassembler option messageAlan Modra6-171/+164
This is the binutils fix for PR 33384. Here we are assuming that no const char* comma-separated option strings are passed in to disassemble_info.disassembler_options. That is true for current usage in gdb and binutils. In fact, there is only one place that passes a string in read-only memory, gdb/tdep-i386.c:disassembly_flavor, and that one is a single option. include/ * dis-asm.h (struct disassemble_info): Comment. (disassembler_options_cmp, next_disassembler_option), (FOR_EACH_DISASSEMBLER_OPTION): Delete. (for_each_disassembler_option): Declare. opcodes/ * disassemble.c (disassembler_options_cmp): Delete. (for_each_disassembler_option): New function. * arc-dis.c (parse_option): Replace disassembler_options_cmp with strcmp. (parse_cpu_option): Likewise. (parse_disassembler_options): Replace FOR_EACH_DISASSEMBLER_OPTION with for_each_disassembler_option, and extract loop body to.. (arc_parse_option): ..this new function. * arm-dis.c (parse_arm_disassembler_options): Delete, extracting loop body to.. (arm_parse_option): ..this new function. (print_insn): Use for_each_disassembler_option. * csky-dis.c (parse_csky_dis_options): Delete, extracting loop body to.. (parse_csky_option): ..this new function. (print_insn_csky): Use for_each_disassembler_option. * nfp-dis.c (parse_disassembler_options): Replace FOR_EACH_DISASSEMBLER_OPTION with for_each_disassembler_option, and extract loop body to.. (nfp_parse_option): ..this new function. Use opcodes_error_handler here rather than info->fprintf_func to print error. * ppc-dis.c (ppc_parse_cpu): Replace disassembler_options_cmp with strcmp. (struct ppc_parse_data): New. (powerpc_init_dialect): Adjust to use new struct. Replace FOR_EACH_DISASSEMBLER_OPTION with for_each_disassembler_option, and extract loop body to.. (ppc_parse_option): ..this new function.
2025-09-25Binutils: Add clang LTO support to AR and RANLIBH.J. Lu3-15/+395
Detect the clang plugin file and and pass it to --plugin for ar and ranlib so that binutils can be built with clang LTO. bfd/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. binutils/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. gas/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. gprof/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. * testsuite/Makefile.in: Likewise. gprofng/ PR binutils/33470 * Makefile.am (ACLOCAL_AMFLAGS): Add -I ../config. * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. * gp-display-html/Makefile.in: Likewise. * libcollector/Makefile.in: Likewise. * libcollector/aclocal.m4: Likewise. * libcollector/configure: Likewise. * src/Makefile.in: Likewise. * libcollector/Makefile.am (ACLOCAL_AMFLAGS): Add -I ../../config. ld/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. libctf/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. libsframe/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. opcodes/ PR binutils/33470 * Makefile.in: Regenerated. * aclocal.m4: Likewise. * configure: Likewise. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-09-23aarch64: Update system register gatingAlice Carlotti1-485/+485
Historically we have been inconsistent and overly restrictive in our choice of features to gate system register accesses. (Originally this gating was always applied, but now it is disabled unless the --menable-sysreg-checking option is specified). This patch updates these constraints, following the principle that we should only reject a system register access if it requires some architecture feature or version whose corresponding command line extension has not been enabled. The most common change in this patch concerns system registers that were: - part of a feature FEAT_X with no corresponding command line extension; - introduced in a newer architecture version ArmvX.Z; - permitted to be implemented from an earlier version ArmvX.Y. Previously these system registers tended to be gated on ArmvX.Z or left ungated, but following the above principle they are now gated on ArmvX.Y instead.
2025-09-23aarch64: Remove CSRE system registersAlice Carlotti1-12/+0
Most support for CSRE was removed from Binutils in 2021 after it was removed from the architecture. This patch removes the remaining system registers and test files.
2025-09-23aarch64: Remove teecr32_el1 and teehbr32_el1Alice Carlotti1-2/+0
These system registers were removed from the architecture over a decade ago, so there's no need to continue supporting them.
2025-09-23aarch64: Add missing system registersAlice Carlotti1-0/+9
This adds all of the system registers present in the 2025-03 release of the Architecture Registers spec (DDI0601) that were missing from Binutils.
2025-09-23aarch64: Add FEAT_SRMASK system registersAlice Carlotti1-0/+24
2025-09-23aarch64: Make spmzr_el0 write-onlyAlice Carlotti1-1/+1
Remove all test cases that expect spmzr_el0 to be readable, and remove some redundant default macro values from armv9_5-a-sysregs.s while we're there. Add a read of spmzr_el0 to sysreg-diagnostics.s. This turns out to be the first test for the "reading from a write-only register" note. Also remove the recently added -menable-sysreg-checking option from this test, both to simplify the addition of spmzr_el0 to the test, and to verify that read/write diagnostics don't depend on that option.
2025-09-23aarch64: Sort aarch64-sys-regs.defAlice Carlotti1-14/+14
Fix obvious alphabetisation errors, and move s2pir_el2 and s2por_el1 to the start of the "s" section to match the ordering in the Arm ARM.
2025-09-23aarch64: Remove F_ARCHEXT flagAlice Carlotti3-1290/+1282
The flag is unnecessary, because we can just unconditionally check the features field every time. Having the information duplicated in two separate fields makes it harder to maintain, particularly in the context of the upcoming regating patch. The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now unused, so remove that as well.
2025-09-18Updated and new translations for the binutilsNick Clifton1-220/+228
2025-09-03csky disassembler leakAlan Modra1-0/+1
* csky-dis.c (parse_csky_dis_options): Free copy of options.
2025-09-02PowerPC: Vector Instructions for Deeply Compressed Weight for AI (RFC02691)Abhay Kandpal1-0/+22
opcodes/ * ppc-opc.c: (VXSEL5, VXSEL4, VXSEL3, VXSEL2, UIMM1): New defines. (powerpc_opcodes): <vucmprhn, vucmprln, vucmprhb, vucmprlb, vucmprhh, vucmprlh, vupkhsntob, vupklsntob, vupkint4tobf16, vupkint8tobf16, vupkint4tofp32, vupkint8tofp32>: New instructions. gas/ * gas/testsuite/gas/ppc/future.s: Add new testcases. * gas/testsuite/gas/ppc/future.d: Likewise.
generated by cgit v1.1 at 2025-12-26 13:25:51 +0000