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2026-02-06Updated/new translation files for the 2.46 releaseNick Clifton6-921/+3246
2026-02-05bpf: add may_goto instruction [PR32176]David Faust1-0/+4
The BPF "may_goto" instruction is a special sort of conditional jump where the condition is determined by the BPF runtime. That is, it is a no-op until the runtime decides otherwise. For normal asm syntax, the mnemonic "jcond" is chosen in keeping with the style of following the opcode definitions in the Linux kernel uapi BPF headers. This instruction is not currently emitted by GCC, but it can be inserted into BPF programs via macros defined in the Linux kernel. PR gas/32176 include/ * opcode/bpf.h (BPF_CODE_JCOND): New. (bpf_insn_id): Add BPF_INSN_JCOND. opcodes/ * bpf-opc.c: Add entry for BPF_INSN_JCOND. gas/testsuite/ * gas/bpf/bpf.exp: Run new dump tests. * gas/bpf/jcond-be-pseudoc.d: New. * gas/bpf/jcond-be.d: New. * gas/bpf/jcond-pseudoc.d: New. * gas/bpf/jcond-pseudoc.s: New. * gas/bpf/jcond.d: New. * gas/bpf/jcond.s: New.
2026-02-05PowerPC: Support for Elliptic Curve Cryptography Instructions (RFC02669)Abhay Kandpal1-7/+81
opcodes/ * ppc-opc.c: (insert_s3, extract_s3): New functions. (PSSUMEXT, S1EXP, PSSUM, S0EXP, SFUNC, S2EXP, VMSOP, P_VMS_MASK, XX3MADD_MASK, XX3MUL_MASK, XX3SUM_MASK): New defines. (PS, PSD): Update for new macros. (powerpc_opcodes): Add xxmulmul, xxmulmulhiadd, xxmulmulloadd, xxssumudm, xxssumudmc, xsmerge2t3uqm, xsaddadduqm, xsaddaddsuqm, xsaddsubuqm, xsmerge3t1uqm, xsrebase2t1uqm, xsrebase2t2uqm, xsrebase3t3uqm, xsrebase2t3uqm, xsrebase2t4uqm, xsaddsubsuqm, xsmerge2t1uqm, xsmerge2t2uqm, xsrebase3t1uqm, xsrebase3t2uqm, xxssumudmcext. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2026-02-04aarch64: fix buffer overflow in aarch64-genMatthieu Longo1-1/+1
A refactoring in [1] introduced a buffer overflow. A new enum value, last_iclass, was added at the end of 'enum aarch64_insn_class' to refer to the last instruction class. This value is then used to size the array iclass_has_subclasses_p, which is intended to have one element per enum value. However, because the enum values start at index 0, last_iclass is off by one when used as the array length. As a result, the array is allocated with element too few, leading to a buffer overflow when accessing the 'lut' class. The fix adds +1 to last_iclass when defining the array size. ==ERROR: AddressSanitizer: global-buffer-overflow READ of size 1 at 0x5555556d8d5d thread T0 #0 0x5555555c918d in read_table ./opcodes/aarch64-gen.c:207 #1 0x5555555ca0d1 in initialize_decoder_tree ./opcodes/aarch64-gen.c:435 #2 0x5555555ceaa6 in main ./opcodes/aarch64-gen.c:1386 [1]: 002ac0590221a01463a1eb92e2f0d81f616a4959
2026-01-29Update version now that the 2.46 branch has been createdNick Clifton1-10/+10
2026-01-28regen pot filesAlan Modra1-1/+1
2026-01-26regen pot filesAlan Modra1-9/+9
2026-01-25Regenerate autogenerated filesNick Clifton1-152/+156
2026-01-24aarch64: Remove redundant macrosAlice Carlotti2-6/+1
We no longer encode flags in the aarch64_hint_options value field, so delete the HINT_VAL, HINT_FLAG and HINT_ENCODE macros.
2026-01-24aarch64: Add support for TLBID system registersSrinath Parvathaneni1-0/+9
This patch adds support for following TLBID system registers. * tlbididr_el1 (RO) * vtlbid0_el2 * vtlbid1_el2 * vtlbid2_el2 * vtlbid3_el2 * vtlbidos0_el2 * vtlbidos1_el2 * vtlbidos2_el2 * vtlbidos3_el2
2026-01-24aarch64: TLBI Domains changes for PLBI instructionSrinath Parvathaneni1-28/+37
For the PLBI instruction with optional register argument <Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to have an Rt value which is not 0b11111 and this is allowed for all the TLBI instructions with a <type> of ALLE1*, ALLE2* and VMALL* and a <shareability> of IS or OS.
2026-01-24aarch64: Enable TLBIP instructions with tlbid optionSrinath Parvathaneni2-41/+69
TLBI Domains feature changes TLBI and TLBIP system instructions. For all TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS* instructions that are currently dependent on FEAT_D128 (+d128), will also be available with FEAT_TLBID (+tlbid).
2026-01-24aarch64: Add support for FEAT_TLBID featureSrinath Parvathaneni3-28/+60
TLBI Domains feature changes TLBI and TLBIP system instructions. For the TLBI instruction with optional register argument <Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to have an Rt value which is not 0b11111 and this is allowed for all the TLBI instructions with a <type> of ALLE1*, ALLE2*, VMALL*, VMALLS12* or VMALLWS2* and a <shareability> of IS or OS. This patch add support for FEAT_TLBID feature, which is enabled by new +tlbid option.
2026-01-24opcodes: Fix branch displacement mask in M*Core disassemblerMichal Sobon1-1/+1
The BT, BF, BR, and BSR instructions use the Scaled 11-Bit Displacement addressing mode. According to the Motorola M*Core Reference Manual, the instruction format has: - bits 15-11: opcode - bits 10-0: 11-bit signed displacement field The displacement calculation is: PC <- PC + 2 + (sign-extended disp11 << 1) The disassembler was incorrectly masking with 0x3FF (10 bits) instead of 0x7FF (11 bits). This masked off bit 10, which is the sign bit for the 11-bit signed displacement. As a result, negative (backward) branches were incorrectly disassembled as forward branches. opcodes/ * mcore-dis.c (print_insn_mcore): Fix displacement mask from 0x3FF to 0x7FF in BR case to correctly extract all 11 bits including the sign bit. Signed-off-by: Michal Sobon <msobon@hex-rays.com>
2026-01-21opcodes: Fix BMASKI disassembly for immediate 32 on M*CoreMichal Sobon1-1/+4
The BMASKI instruction has three encoding variants (OMa, OMb, OMc). The OMa encoding (0x2C00, mask 0xFFF0) specifically represents BMASKI with immediate 32, encoded as IMM5=0. Per Motorola M*Core specification: "An IMM5 value of 0 is interpreted as a value of 32." Previously, all three variants extracted the immediate the same way, causing OMa to incorrectly display 0 instead of 32. Before: 0x2c04 -> bmaski r4, 0 After: 0x2c04 -> bmaski r4, 32 opcodes/ * mcore-dis.c (print_insn_mcore): Handle OMa encoding to display immediate 32 instead of 0 for BMASKI. gas/testsuite/ * gas/mcore/allinsn.s: Add test for bmaski with immediate 32. Replace two clrc padding instructions with one for 4-byte alignment. Fix missing newline at end of file. * gas/mcore/allinsn.d: Update expected output. Signed-off-by: Michal Sobon <msobon@hex-rays.com>
2026-01-19MIPS/opcodes: Fix floor/round exclusions for R5900David Guillen Fandos1-2/+2
MIPS R5900 does not feature ceil/floor/round instructions, but only ceil is correctly excluded at the moment. Correct the other two. Signed-off-by: David Guillen Fandos <david@davidgf.net>
2026-01-16aarch64: Add support for FEAT_MTETCRichard Ball1-0/+2
This patch adds two new DC operations: *gbva *zgbva
2026-01-16aarch64: Add FEAT_SCR2 System registersRichard Ball1-0/+1
This patch adds the system register "SCR2_EL3" Defined by FEAT_SCR2.
2026-01-16aarch64: Add support for FEAT_CMHRichard Ball6-1/+28
This patch adds the new instructions from FEAT_CMH These new instructions are hints, STCPH and SHUH. SHUH can have an operand PH or no operand.
2026-01-16arm: Fix MVE vmlas encodingRichard Ball1-1/+1
Continuation of fix to VMLA Bit 12 of the first halfword in the VMLAS instruction is listed as (0) in the ARMARM (document DDI0553B.w, version ID07072023). This means that the instruction does not discriminate between signed and unsigned types and processing elements do not use the bit. The encoding used by gas was based on an older version of the document that made the sign important. This change makes it possible to use vmlas.i8 (16,32) in addition to vmlas.u8 and vmlas.s8 mnemonics, with the i8, i16 and i32 aliases becoming the default when disassembling. The generated encoding sets bit 12 to 0, compatibly with other assembler implementations.
2026-01-16aarch64: Add support for MLBI system instructionsRichard Ball7-0/+27
This patch adds support for MLB invalidate (MLBI) instruction. Syntax: MLBI <mlbi_op>{, <Xt>} This instruction is an alias to "SYS #4, C7, C0, #<op2>{, <Xt>}" and MLBI being the preferred disassembly. The following list of MLBI operations are supported in this patch for the MLBI instructions enabled by "+mpamv2" * alle1 * vmalle1 * vpide1 * vpmge1
2026-01-16aarch64: Add FEAT_MPAMv2_VID system registersRichard Ball1-0/+3
This patch adds the system registers defined by FEAT_MPAMv2_VID. These registers are: *mpamvidcr_el2 *mpamvidsr_el2 *mpamvidsr_el3
2026-01-16aarch64: Add FEAT_MPAMv2 system registersEzra Sitorus1-0/+4
2026-01-13PowerPC: Support for eTCE (RFC02662)Abhay Kandpal1-0/+13
opcodes/ * ppc-opc.c (XTLBIE_MASK, XTLBIEIO_MASK): New macros. (powerpc_opcodes): Add tlbiep, tlbieio, tlbsyncio, ptesyncio. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2026-01-12PowerPC: Support for Additional Performance Monitor Counters (RFC02666)Abhay Kandpal1-0/+22
opcodes/ * ppc-opc.c (powerpc_opcodes): Add mtummcrae, mtummcr2e, mtmmcr2e, mtmmcrae, mtmmcr1e, mtmmcr3e, mtupmc7, mtupmc8, mtpmc7, mtpmc8, mfummcrae, mfmmcrae, mfummcr1e, mfmmcr1e, mfummcr2e, mfmmcr2e, mfummcr3e, mfmmcr3e, mfupmc7, mfpmc7, mfupmc8, mfpmc8. gas/ * testsuite/gas/ppc/future.s: New test. * testsuite/gas/ppc/future.d: Likewise.
2026-01-09x86: optimize MOVZX in a few casesJan Beulich2-6/+6
There are shorter encoding options available, so space optimization is possible.
2026-01-09x86: optimize MOVSX between accumulator regsJan Beulich2-12/+12
Except on the K6 CBW/CWDE/CDQE perform equally well, but are shorter to encode.
2026-01-07aarch64: Add FEAT_NV3, FEAT_SRMASK2 system registersEzra Sitorus1-0/+6
2026-01-07aarch64: Add support for FEAT_TPS and FEAT_TPSP system registersSrinath Parvathaneni1-0/+16
This patch adds support for TPMIN*/TPMAX* system registers as part of POE2 extension.
2026-01-05aarch64: Add support for POE2 PLBI instructionSrinath Parvathaneni7-1/+51
This patch adds support for PLB invalidate operation (PLBI) instruction and the corresponding system registers as operand (<plbi_op>). Syntax: PLBI <plbi_op>{, <Xt>} This instruction is an alias to "SYS #<op1>, C10, <Cm>, #<op2>{, <Xt>}" and PLBI being the preferred disassembly. The following list of system registers are supported in this patch for the PLBI instructions enabled by "+poe2" flag and also the "nxs" variants of these system registers are enabled by "+poe2+xs" flag. * alle1 * alle1is * alle1os * alle2 * alle2is * alle2os * alle3 * alle3is * alle3os * aside1 * aside1is * aside1os * permae1 * permae1is * permae1os * perme1 * perme1is * perme1os * perme2 * perme2is * perme2os * perme3 * perme3is * perme3os * vmalle1 * vmalle1is * vmalle1os
2026-01-05aarch64: Add support for TEV instructionsSrinath Parvathaneni6-11/+48
This patch adds support for FEAT_TEV feature enabled by "+tev" flag along with support for following instructions. * TENTER * TEXIT TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED_17 operand to handle the not_balanced (NB) argument , where as a new operand AARCH64_OPND_NOT_BALANCED_10 is added to support the NB (not_balanced) argument in TEXIT instruction.
2026-01-05aarch64: Add support for POE2 system registersSrinath Parvathaneni1-0/+264
This patch adds support for POE2 system registers which are available by default, however if guarding restrictions are enabled using -menable-sysreg-checking than "+poe2" option need to specified to the -march. Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com>
2026-01-05aarch64: Add support for POE2 instructionsSrinath Parvathaneni6-14/+85
This patch adds support for FEAT_S1POE2 feature enabled by "+poe2" flag along with support for following instructions. * TCHANGEB (immediate) * TCHANGEB (register) * TCHANGEF (immediate) * TCHANGEF (register) A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this patch to support the new optional argument "NB" (not_balanced) which is a 1-bit field in the encoding for all the above mentioned instructions. Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com>
2026-01-01Update year range in copyright notice of binutils filesAlan Modra273-277/+277
Avoid warnings about invalid escapes in etc/update-copyright.py by using raw strings, add BinutilsFilter to skip psql.rc and add "Kalray SA." as another copyright holder.
2025-12-29aarch64: Remove sme2_movaz instruction classAlice Carlotti3-23/+21
The behaviour of sme2_movaz was identical to sme_misc, so use that instead.
2025-12-29aarch64: Remove a space from movaz za operandAlice Carlotti1-27/+14
The za operands of most movaz instructions were originally printed with an extra space compared to other za operands. Remove this space, and reduce code duplication in the process.
2025-12-29aarch64: Accept .b/.h/.s in movaz (array to vector)Alice Carlotti1-2/+2
While the .d form is preferred for disassembly, assemblers should accept any element size that is used consistently. The sme2_mov class handles this already for mov instructions, so use that here as well.
2025-12-29aarch64: Fix luti2/luti4 decode maskAlice Carlotti1-3/+3
Neither the opcode mask nor the size determination were checking bit 13, so some undefined opcodes were being incorrectly disassembled as valid luti2/luti4 instructions.
2025-12-27AArch64 v9.7 extensions: FEAT_SVE_B16MMSivan Shani3-4/+23
This patch includes: - Feature flag for FEAT_SVE_B16MM - Instruction: - BFMMLA (non-widening) BFloat16 matrix multiply-accumulate.
2025-12-27AArch64 v9.7 extensions: FEAT_F16MMSivan Shani3-8/+50
This patch includes: - Feature flag for FEAT_F16MM - Instructions: - FMMLA (non-widening) Half-precision matrix multiply-accumulate - FMMLA (non-widening) Floating-point matrix multiply-accumulate
2025-12-27AArch64: Add FEAT_F16F32MMSivan Shani3-7/+26
This patch includes: - The feature flag for the FEAT_F16F32MM feature. - Instruction FMMLA Half-precision matrix multiply-accumulate to single-precision.
2025-12-27AArch64: Add FEAT_F16F32DOT instructionsSivan Shani3-11/+42
This includes the instructions for the F16F32DOT feature: - FDOT half-precision to single-precision, by element - FDOT half-precision to single-precision, vector
2025-12-27AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.Sivan Shani11-85/+531
This patch includes: - Flags for the FEAT_SVE2p3 and FEAT_SME2p3 features. - Instructions: - ADDQP - ADDSUBP - FCVTZSN - FCVTZUN - LUTI6 16-bit - LUTI6 8-bit - SABAL - SCVTF - SCVTFLT - SDOT vectors - SDOT indexed - SQRSHRN - SQRSHRUN - SQSHRN - SQSHRUN - SUBP - UABAL - UCVTF - UCVTFLT - UDOT vectors - UDOT indexed - UQRSHRN - UQSHRN - LUTI6 vector - LUTI6 table, four registers - LUTI6 table, single, 8-bit In addition, new operands: - OPND_SME_Zmx2_INDEX_22: an operand represents a list of vector registers with an index. - OPND_SME_Zn7xN_UNTYPED: an operand represents an untyped list of vector registers.
2025-12-27aarch64: Add FEAT_MOPS_GO instructionsYury Khrustalev4-4/+197
Also add +mops-go feature flag and make the mops-go feature depend on the memtag and mops features.
2025-12-20LoongArch: Add disassembly support for ud ui5Lulu Cai2-3/+33
ud ui5, also known as amswap.w rd,$r1,rj(rd==rj), is displayed as "ud ui5" by default during disassembly. Alternatively, the original instruction can be printed using the objdump -M no-aliases. To implement this support, a format specifier "ru0:5,ru5:5" for ud is applied exclusively during disassembly. This specifier indicates that registers should be printed using their corresponding numeric values, and when the instruction is identified as ud, only a single parameter is displayed. binutils/ * testsuite/binutils-all/loongarch64/dis-amswap-ud-noaliases.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.s: New test. gas/ * testsuite/gas/loongarch/macro_ud.d: Update test. include/ * opcode/loongarch.h: New macro. opcodes/ * loongarch-dis.c (get_loongarch_opcode_by_binfmt): Correct match `ud`. (dis_one_arg): Disassemble the `ud` parameter. * loongarch-opc.c: Add opcode for "ud" alias.
2025-12-19bfin: avoid gcc extension using __VA_ARGS__Jan Beulich1-1/+1
We shouldn't be using extensions when we don't have a suitable fallback in place. For cases where there's no argument wanted, OUTS() already exists.
2025-12-15aarch64: Add support for new BTI <target> "r"Srinath Parvathaneni4-9/+5
This patch adds support for new BTI <target> "r" (instruction: bti r), which is an alias to "bti" (with no target), for both "bti" and "bti r" the preferred disassembly is "bti r". This "bti r" instruction is by default available from Armv8-A architecture. The HINT_OPD_F_NOPRINT macro has become redundant with these changes and has been removed.
2025-12-15Arc: use generic BFD_RELOC_... in favor of custom typesJan Beulich1-1/+1
No reason to have separate types when the generic ones have no (other) meaning for this target.
2025-12-11aarch64: Add support for FEAT_LSCPRichard Ball3-8/+50
This patch adds the new instructions from FEAT_LSCP. These instructions are LDAP, LDAPP and STLP.
2025-12-10LoongArch: LA32 macros supportmengqinggang1-20/+57
Change pcalau12i to pcaddu12i for LA32 macros. Add call/tail and call30/tail30 macros, call/tail can expand to call36/tail36 or call30/tail30 by mabi option.
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