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7 daysaarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
8 daysRISC-V: Support for unlabeled landing pad PLT generationKito Cheng1-0/+1
This patch adds support for generating unlabeled landing pad PLT entries for the RISC-V architecture. Unlabeled landing pad will place a LPAD instruction at the PLT entry and PLT header, also PLT header will have few changes due to the offset is different from the original one. Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
8 daysRISC-V: Add GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS and ↵Kito Cheng1-0/+5
GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED This patch adds two new GNU properties for RISC-V: GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS and GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED. We only add readelf and define the properties in this patch. Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
12 daysaarch64: Support for FEAT_LSFEEzra Sitorus1-2/+7
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
12 daysaarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
12 daysaarch64: Support for FEAT_CMPBREzra Sitorus1-0/+5
FEAT_CMPBR - Compare and branch instructions. This patch adds these instructions: - CB<CC> (register) - CB<CC> (immediate) - CBH<CC> - CBB<CC> where CC is one of the following: - EQ - NE - GT - GE - LT - LE - HI - HS - LO - LS
13 daysaarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+2
FEAT_OCCMO support was introduced, but the feature flags were missing. This patch adds these flags, as well as splitting up the tests to test occmo vs occmo+memtag operands.
13 daysaarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+5
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE and BFMUL.
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+4
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-06-11aarch64: Add definitions for missing architecture bitsYury Khrustalev1-4/+16
Complete macros for feature bits for v9.1-A, v9.2-A, v9.3-A, and v9.4-A.
2025-06-11kvx gcc-4.5 build fixesAlan Modra1-2/+2
More missing struct initialisers, for expressionS vars that in this case don't need to be initialised. Also an error: redefinition of typedef 'symbolS'. OK, so don't use a typedef.
2025-06-09aarch64: Increase the number of feature words to 3Richard Earnshaw1-1/+2
Now that most of the effort of updating the number of feature words is handled by macros, add an additional one, taking the number of supported features to 192.
2025-06-09aarch64: use macro trickery to automate feature array size replicationRichard Earnshaw1-36/+87
There are quite a few macros that need to be changed when we need to increase the number of words in the features data structure. With some macro trickery we can automate most of this so that a single macro needs to be updated. With C2X we could probably do even better by using recursion, but this is still a much better situation than we had previously. A static assertion is used to ensure that there is always enough space in the flags macro for the number of feature bits we need to support.
2025-06-09aarch64: Fix typos in opcode headersYury Khrustalev1-4/+4
2025-05-22RISC-V: Add support for Smcdeleg and Ssccfg extensions.Jiawei1-0/+4
This patch rebases the original patch from Nelson's implement[1]. Added new extension Smcdeleg and Ssccfg with a new CSR, scountinhibit.[2] Co-Authored-By: Nelson Chu <nelson@rivosinc.com> Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn> [1] https://patchwork.sourceware.org/project/binutils/patch/20240620045359.47513-1-nelson@rivosinc.com/ [2] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Mention new extensions. * config/tc-riscv.c (enum riscv_csr_class): New CSR class. (riscv_csr_address): Add support for Ssccfg. * testsuite/gas/riscv/csr-version-1p10.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr.s: New Ssccfg CSR. * testsuite/gas/riscv/imply.d: New imply check. * testsuite/gas/riscv/imply.s: New implies. * testsuite/gas/riscv/march-help.l: New helping info. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTINHIBIT): New CSR address. (DECLARE_CSR): Add Ssccfg CSR.
2025-05-20libiberty: sync with gccAndreas Schwab1-0/+22
Import the following commits from GCC as of r16-614-g9d039eff453f77: 31dd621796f libiberty: add ldirname function f3d07779fdb libiberty: Append <libgen.h> to AC_CHECK_DECLS [PR119218]. 90183362524 libiberty, gcc: Add memrchr to libiberty and use it [PR119283]. 43717ee9064 libiberty: Fix off-by-one when collecting range expression
2025-05-16RISC-V: Add zilsd & zclsd supportdysun1-0/+2
Ref: https://github.com/riscv/riscv-zilsd/blob/main/zilsd.adoc Signed-off-by: dysun <sundongya@nucleisys.com> Co-developed-by: LIU Xu <liuxu@nucleisys.com> Co-developed-by: ZHAO Fujin <zhaofujin@nucleisys.com>
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti1-6/+10
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei1-0/+4
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and 'hedelegh'. More details between 1.12 and 1.13 see [1]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc Version log: Remove gas/po changes. bfd/ChangeLog: * cpu-riscv.c: New option. * cpu-riscv.h (enum riscv_spec_class): Ditto. binutils/ChangeLog: * doc/binutils.texi: New option. gas/ChangeLog: * NEWS: Add priv-1.13 support. * config/tc-riscv.c: New option. * configure: Ditto. * configure.ac: Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning. * testsuite/gas/riscv/csr-version-1p11.d: New CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning. * testsuite/gas/riscv/csr-version-1p12.d: New CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning. * testsuite/gas/riscv/csr.s: New CSR. * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/csr-version-1p13.d: New test. * testsuite/gas/riscv/csr-version-1p13.l: New test. include/ChangeLog: * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. (CSR_HEDELEGH): Ditto. (DECLARE_CSR): Ditto.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu2-0/+69
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-04-07xcoff dynamic symbol string sanityAlan Modra1-12/+12
Sanity check symbol string table offsets, and tidy structs. "long" isn't a good choice for _l_zeroes and _l_offset since it can be 64 bits which blows out the size of the symbol struct unnecessarily. Also, all of the sizes in internal_ldsym need only be 32 bits, but I made them size_t because I didn't want to audit all expressions using them for overflow. bfd/ * xcofflink.c (_bfd_xcoff_canonicalize_dynamic_symtab): Sanity check symbol _l_offset. (xcoff_link_add_dynamic_symbols), (xcoff_link_check_dynamic_ar_symbols): Likewise. include/ * coff/xcoff.h (struct internal_ldhdr): Tidy types. (struct internal_ldsym): Use uint32_t for _l_zeroes and _l_offset.
2025-03-26RISC-V: add Smrnmi 1.0 instruction supportJerry Zhang Jian2-0/+6
Add instruction `mnret' support Ref: https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi bfd/ChangeLog: * elfxx-riscv.c: Add new Smrnmi instruction class handling gas/ChangeLog: * testsuite/gas/riscv/smrnmi.s: New test for mnret * testsuite/gas/riscv/rmrnmi.d: Likewise include/ChangeLog: * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET * opcode/riscv.h: Add new instruction class opcodes/ChangeLog: * riscv-opc.c: Add `mnret' instruction Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma2-0/+16
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-10Revert past commitsSimon Marchi2-100/+92
I accidentally pushed my work-in-progress branch... revert that. Sorry for the noise :(. The list of commits reverted are: ae2a50a9ae15 attempt to revamp to the CU/TU list e9386435c94f gdb/dwarf: print DWARF CUs/TUs in "maint print objfiles" 6cbd64aa3eb0 gdb/dwarf: add dwarf_source_language_name 32a187da7622 libiberty: move DW_LANG_* definitions to dwarf2.def b3fa38aef59d gdb/dwarf: move index unit vectors to debug names reader and use them 30ba74418982 gdb/dwarf: track comp and type units count bedb4e09f292 gdb/dwarf: remove unnecessary braces b4f18de12c77 gdb/dwarf: use ranged for loop in some pots Change-Id: I80aed2847025f5b15c16c997680783b39858a703
2025-03-10libiberty: move DW_LANG_* definitions to dwarf2.defSimon Marchi2-92/+100
In order to get a "DW_LANG_* to string" function: - move the "DW_LANG_*" definitions from dwarf2.h to dwarf2.def - add the necessary macros in dwarf2.h to generate the enumeration - add the necessary macros in dwarfnames.c to generate the "to string" function include/ChangeLog: * dwarf2.h (DW_LANG, DW_FIRST_LANG, DW_END_LANG): Define then undefine. (enum dwarf_source_language): Remove. (get_DW_LANG_name): Declare. * dwarf2.def: Define DW_LANG_* constants. libiberty/ChangeLog: * dwarfnames.c (DW_FIRST_LANG, DW_END_LANG, DW_LANG): Define then undefine. Change-Id: I440aa2b1f55c7585d7e44c8fa7c41310b0ef2b3a Cc: binutils@sourceware.org
2025-03-07include: drop bout.hJan Beulich1-192/+0
gas'es obj-bout.c was dropped about 20 years ago, while bfd's bout.c was dropped almost 7 years ago. Time for the unused header to go away, too.
2025-03-04clean-up aarch64: move the name of the build attributes section into ↵Matthieu Longo1-0/+2
include/elf/aarch64.h
2025-03-03RISC-V: Support ssqosid extension with version 1.0.Kito Cheng1-0/+4
It only add one new CSR: `srmcfg`. Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
2025-02-18PR 32603, more ld -w misbehaviourAlan Modra1-0/+3
Commit 8d97c1a53f3d claimed to replace all einfo calls using %F with a call to fatal. It did so only for the ld/ directory. This patch adds a "fatal" to linker callbacks, and replaces those calls in bfd/ too.
2025-01-19Add markers for bihnutils 2.44 branchNick Clifton1-0/+4
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti1-2/+8
Many FEAT_SVE2p1 instructions need to be enabled by either of two different features (one for streaming mode, and one for non-streaming mode). This patch adds correct gating conditions for these instructions. There were also a few sve2p1 instructions missing altogether, so add those as well. The testsuite is modified to check for all alternative enablement conditions. In many cases this is done by adding an alternative assembler commands to existing test files. For some SME/SME2 tests, only some of the instructions are enabled by +sve2p1, so these are copied into a separate test. For original SVE2p1 tests, the non-SME2p1 instructions have been moved to a separate test file. There are also new tests for the newly added instructions. These include a couple of fixme comments relating to bad error reporting, which should be investigated later.
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang2-0/+36
https://github.com/riscv/riscv-cfi/releases/tag/v1.0 This patch only support the CFI instructions and CSR in assembler.
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu2-3/+18
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 The privileged spec v1.10 already removed the sfence.vm instruction, and the encoding of sfence.vm instruction is overlapped with the sctrclr instruction of ssctr/smctr. But since the privileged spec v1.10 already removed the sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we had to remove the sfence.vm. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr. (riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0. (riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address): Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR. (riscv_is_priv_insn): Removed SFENCE_VM check. * testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no longer supported since privileged spec v1.10. * testsuite/gas/riscv/attribute-14.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr. * testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction. * testsuite/gas/riscv/smctr-ssctr.s: Likewise. include/ * opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed encoding macro for sfence.vm since encoding conflict. Added CSR numbers for ssctr/smctr CSRs. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SMCTR_OR_SSCTR for sctrclr. opcodes/ * riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm since encoding conflict.
2025-01-14elf: Add GNU_PROPERTY_MEMORY_SEAL gnu propertyAdhemerval Zanella2-0/+4
The GNU_PROPERTY_MEMORY_SEAL gnu property is a way to mark binaries to be memory sealed by the loader, to avoid further changes of PT_LOAD segments (such as unmapping or change permission flags). This is done along with Linux kernel (the mseal syscall [1]), and C runtime supports to instruct the kernel on the correct time during program startup (for instance, after RELRO handling). This support is added along the glibc support to handle the new gnu property [2]. This is a opt-in security features, like other security hardening ones like NX-stack or RELRO. The new property is ignored if present on ET_REL objects, and only added on ET_EXEC/ET_DYN if the linker option is used. A gnu property is used instead of DT_FLAGS_1 flag to allow memory sealing to work with ET_EXEC without PT_DYNAMIC support (at least on glibc some ports still do no support static-pie). [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8be7258aad44b5e25977a98db136f677fa6f4370 [2] https://sourceware.org/pipermail/libc-alpha/2024-September/160291.html Change-Id: Id47fadabecd24be0e83cff45653f7ce9a900ecf4
2025-01-14aarch64 DWARF: add new CFI directive for PAuth_LRMatthieu Longo1-0/+2
This patch adds a new CFI directive (cfi_negate_ra_state_with_pc) which set an additional bit in the RA state to inform that RA was signed with SP but also PC as an additional diversifier. RA state | Description 0b00 | Return address not signed (default if no cfi_negate_ra_state*) 0b01 | Return address signed with SP (cfi_negate_ra_state) 0b10 | Invalid state 0b11 | Return address signed with SP+PC (cfi_negate_ra_state_with_pc) Approved-by: Indu Bhagat <indu.bhagat@oracle.com> Approved-by: Jan Beulich <jbeulich@suse.com>
2025-01-14ld: Add LTO and none-LTO output support for ld -rH.J. Lu1-0/+1
Link with mixed IR/non-IR objects * 2 kinds of object files o non-IR object file has * non-IR sections o IR object file has * IR sections * non-IR sections * The output of "ld -r" with mixed IR/non-IR objects should work with: o Compilers/linkers with IR support. o Compilers/linkers without IR support. * Add the mixed object file which has o IR sections o non-IR sections: * Object codes from IR sections. * Object codes from non-IR object files. o Object-only section: * With section name ".gnu_object_only" and SHT_GNU_OBJECT_ONLY type on ELF: https://gitlab.com/x86-psABIs/Linux-ABI #define SHT_GNU_OBJECT_ONLY 0x6ffffff8 /* Object only */ * Contain non-IR object file. * Input is discarded after link. * Linker action: o Classify each input object file: * If there is a ".gnu_object_only" section, it is a mixed object file. * If there is a IR section, it is an IR object file. * Otherwise, it is a non-IR object file. o Relocatable non-IR link: * Prepare for an object-only output. * Prepare for a regular output. * For each mixed object file: * Add IR and non-IR sections to the regular output. * For object-only section: * Extract object only file. * Add it to the object-only output. * Discard object-only section. * For each IR object file: * Add IR and non-IR sections to the regular output. * For each non-IR object file: * Add non-IR sections to the regular output. * Add non-IR sections to the object-only output. * Final output: * If there are IR objects, non-IR objects and the object-only output isn't empty: * Put the object-only output into the object-only section. * Add the object-only section to the regular output. * Remove the object-only output. o Normal link and relocatable IR link: * Prepare for output. * IR link: * For each mixed object file: * Compile and add IR sections to the output. * Discard non-IR sections. * Object-only section: * Extract object only file. * Add it to the output. * Discard object-only section. * For each IR object file: * Compile and add IR sections to the output. * Discard non-IR sections. * For each non-IR object file: * Add non-IR sections to the output. * Non-IR link: * For each mixed object file: * Add non-IR sections to the output. * Discard IR sections and object-only section. * For each IR object file: * Add non-IR sections to the output. * Discard IR sections. * For each non-IR object file: * Add non-IR sections to the output. This is useful for Linux kernel build with LTO. bfd/ PR ld/12291 PR ld/12430 PR ld/13298 * bfd.c (bfd_lto_object_type): Add lto_mixed_object. (bfd): Add object_only_section. (bfd_group_signature): New. * elf.c (special_sections_g): Add .gnu_object_only. * format.c: Include "plugin-api.h" and "plugin.h" if BFD_SUPPORTS_PLUGINS is defined. (bfd_set_lto_type): Set type to lto_mixed_object for GNU_OBJECT_ONLY_SECTION_NAME section. (bfd_check_format_matches): Don't check the plugin target twice if the plugin target is explicitly specified. * opncls.c (bfd_extract_object_only_section): New. * plugin.c (bfd_plugin_fake_text_section): New. (bfd_plugin_fake_data_section): Likewise. (bfd_plugin_fake_bss_section): Likewise. (bfd_plugin_fake_common_section): Likewise. (bfd_plugin_get_symbols_in_object_only): Likewise. * plugin.c (add_symbols): Call bfd_plugin_get_symbols_in_object_only and count plugin_data->object_only_nsyms. (bfd_plugin_get_symtab_upper_bound): Count plugin_data->object_only_nsyms. bfd_plugin_get_symbols_in_object_only and add symbols from object only section. (bfd_plugin_canonicalize_symtab): Remove fake_section, fake_data_section, fake_bss_section and fake_common_section. Set udata.p to NULL. Use bfd_plugin_fake_text_section, bfd_plugin_fake_data_section, bfd_plugin_fake_bss_section and bfd_plugin_fake_common_section. Set udata.p to NULL. * plugin.h (plugin_data_struct): Add object_only_nsyms and object_only_syms. * section.c (GNU_OBJECT_ONLY_SECTION_NAME): New. * bfd-in2.h: Regenerated. binutils/ PR ld/12291 PR ld/12430 PR ld/13298 * objcopy.c (group_signature): Removed. (is_strip_section): Replace group_signature with bfd_group_signature. (setup_section): Likewise. * readelf.c (get_os_specific_section_type_name): Handle SHT_GNU_OBJECT_ONLY. gas/ PR ld/12291 PR ld/12430 PR ld/13298 * testsuite/gas/elf/section9.s: Add the .gnu_object_only test. * testsuite/gas/elf/section9.d: Updated. include/ PR ld/12291 PR ld/12430 PR ld/13298 * elf/common.h (SHT_GNU_OBJECT_ONLY): New. ld/ PR ld/12291 PR ld/12430 PR ld/13298 * ld.h (ld_config_type): Add emit_gnu_object_only and emitting_gnu_object_only. * ldelf.c (orphan_init_done): Make it file scope. (ldelf_place_orphan): Rename hold to orig_hold. Initialize hold from orig_hold at run-time. (ldelf_finish): New. * ldelf.h (ldelf_finish): New. * ldexp.c (ldexp_init): Take a bfd_boolean argument to supprt object-only output. (ldexp_finish): Likewise. * ldexp.h (ldexp_init): Take a bfd_boolean argument. (ldexp_finish): Likewise. * ldfile.c (ldfile_try_open_bfd): Call cmdline_check_object_only_section. * ldlang.c: Include "ldwrite.h" and elf-bfd.h. * ldlang.c (cmdline_object_only_file_list): New. (cmdline_object_only_archive_list): Likewise. (cmdline_temp_object_only_list): Likewise. (cmdline_lists_init): Likewise. (cmdline_list_new): Likewise. (cmdline_list_append): Likewise. (print_cmdline_list): Likewise. (cmdline_on_object_only_archive_list_p): Likewise. (cmdline_object_only_list_append): Likewise. (cmdline_get_object_only_input_files): Likewise. (cmdline_arg): Likewise. (setup_section): Likewise. (copy_section): Likewise. (cmdline_fopen_temp): Likewise. (cmdline_add_object_only_section): Likewise. (cmdline_emit_object_only_section): Likewise. (cmdline_extract_object_only_section): Likewise. (cmdline_check_object_only_section): Likewise. (cmdline_remove_object_only_files): Likewise. (lang_init): Take a bfd_boolean argument to supprt object-only output. Call cmdline_lists_init. (load_symbols): Call cmdline_on_object_only_archive_list_p to check if an archive member should be loaded. (lang_process): Handle object-only link. * ldlang.h (lang_init): Take a bfd_boolean argument. (cmdline_enum_type): New. (cmdline_header_type): Likewise. (cmdline_file_type): Likewise. (cmdline_bfd_type): Likewise. (cmdline_union_type): Likewise. (cmdline_list_type): Likewise. (cmdline_emit_object_only_section): Likewise. (cmdline_check_object_only_section): Likewise. (cmdline_remove_object_only_files): Likewise. * ldmain.c (main): Call xatexit with cmdline_remove_object_only_files. Pass FALSE to lang_init, ldexp_init and ldexp_finish. Use ld_parse_linker_script. Set link_info.output_bfd to NULL after close. Call cmdline_emit_object_only_section if needed. (add_archive_element): Call cmdline_check_object_only_section. (ld_parse_linker_script): New. * ldmain.h (ld_parse_linker_script): New. * plugin.c (plugin_maybe_claim): Call cmdline_check_object_only_section on claimed IR files. * scripttempl/elf.sc: Also discard .gnu_object_only sections. * scripttempl/elf64hppa.sc: Likewise. * scripttempl/elfxtensa.sc: Likewise. * scripttempl/mep.sc: Likewise. * scripttempl/pe.sc: Likewise. * scripttempl/pep.sc: Likewise. * emultempl/aarch64elf.em (gld${EMULATION_NAME}_finish): Replace finish_default with ldelf_finish. * emultempl/alphaelf.em (alpha_finish): Likewise. * emultempl/avrelf.em (avr_finish): Likewise. * emultempl/elf.em (ld_${EMULATION_NAME}_emulation): Likewise. * emultempl/ppc32elf.em (ppc_finish): Likewise. * emultempl/ppc64elf.em (gld${EMULATION_NAME}_finish): Likewise. * emultempl/spuelf.em (gld${EMULATION_NAME}_finish): Likewise. * testsuite/ld-plugin/lto-10.out: New file. * testsuite/ld-plugin/lto-10a.c: Likewise. * testsuite/ld-plugin/lto-10b.c: Likewise. * testsuite/ld-plugin/lto-10r.d: Likewise. * testsuite/ld-plugin/lto-4.out: Likewise. * testsuite/ld-plugin/lto-4a.c: Likewise. * testsuite/ld-plugin/lto-4b.c: Likewise. * testsuite/ld-plugin/lto-4c.c: Likewise. * testsuite/ld-plugin/lto-4r-a.d: Likewise. * testsuite/ld-plugin/lto-4r-b.d: Likewise. * testsuite/ld-plugin/lto-4r-c.d: Likewise. * testsuite/ld-plugin/lto-4r-d.d: Likewise. * testsuite/ld-plugin/lto.exp (lto_link_tests): Prepare for "LTO 4[acd]", "lto-4r-[abcd]" and "LTO 10" tests. (lto_run_tests): Add "LTO 4[acd]" and "LTO 10" tests. Build liblto-4.a. Run "lto-4r-[abcd]" tests. Run lto-10r and create tmpdir/lto-10.o. Add test for nm on mixed LTO/non-LTO object. Signed-off-by: H.J. Lu <hjl.tools@gmail.com>
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti1-1/+1
Rename to AARCH64_OPND_SME_ZT0_INDEX_MUL_VL.
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti1-1/+0
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for FEAT_SME_F16F16 feature (Non-widening half-precision FP16 to FP16 arithmetic for SME2), which is enabled using command line flags +sme-f16f16 to -march (which enables both FEAT_SME2 and FEAT_SME_F16F16). There are couple of instructions (fadd and fsub variants) which should be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16. Those instructions are already supported in the current assembler, this patch adds tests for those instructions as well.
2025-01-06RISC-V: Eliminate redundant instruction macroXiao Zeng1-1/+0
include/ChangeLog: * opcode/riscv.h: Eliminate redundant instruction macro M_j. Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
2025-01-01Update year range in copyright notice of binutils filesAlan Modra317-317/+317
2024-12-27LoongArch: Fix resolution of undefined weak hidden/protected symbolsXi Ruoyao1-0/+2
An undefined weak hidden/protect symbol should be resolved to runtime address 0, but we were actually resolving it to link-time address 0. So in PIE or DSO the runtime address would be incorrect. Fix the issue by rewriting pcalau12i to lu12i.w, and pcaddi to addi.w. The latter does not always work because the immediate field of addi.w is narrower, report an error in the case the addend is too large. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-12-22Fix -Wenum-constexpr-conversion in enum-flags.hCarlos Galvez1-9/+0
This fixes PR 31331: https://sourceware.org/bugzilla/show_bug.cgi?id=31331 Currently, enum-flags.h is suppressing the warning -Wenum-constexpr-conversion coming from recent versions of Clang. This warning is intended to be made a compiler error (non-downgradeable) in future versions of Clang: https://github.com/llvm/llvm-project/issues/59036 The rationale is that casting a value of an integral type into an enumeration is Undefined Behavior if the value does not fit in the range of values of the enum: https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#1766 Undefined Behavior is not allowed in constant expressions, leading to an ill-formed program. In this case, in enum-flags.h, we are casting the value -1 to an enum of a positive range only, which is UB as per the Standard and thus not allowed in a constexpr context. The purpose of doing this instead of using std::underlying_type is because, for C-style enums, std::underlying_type typically returns "unsigned int". However, when operating with it arithmetically, the enum is promoted to *signed* int, which is what we want to avoid. This patch solves this issue as follows: * Use std::underlying_type and remove the custom enum_underlying_type. * Ensure that operator~ is called always on an unsigned integer. We do this by casting the input enum into std::size_t, which can fit any unsigned integer. We have the guarantee that the cast is safe, because we have checked that the underlying type is unsigned. If the enum had negative values, the underlying type would be signed. This solves the issue with C-style enums, but also solves a hidden issue: enums with underlying type of std::uint8_t or std::uint16_t are *also* promoted to signed int. Now they are all explicitly casted to the largest unsigned int type and operator~ is safe to use. * There is one more thing that needs fix. Currently, operator~ is implemented as follows: return (enum_type) ~underlying(e); After applying ~underlying(e), the result is a very large value, which we then cast to "enum_type". This cast is Undefined Behavior if the large value does not fit in the range of the enum. For C++ enums (scoped and/or with explicit underlying type), the range of the enum is the entire range of the underlying type, so the cast is safe. However, for C-style enums, the range is the smallest bit-field that can hold all the values of the enumeration. So the range is a lot smaller and casting a large value to the enum would invoke Undefined Behavior. To solve this problem, we create a new trait EnumHasFixedUnderlyingType, to ensure operator~ may only be called on C++-style enums. This behavior is roughly the same as what we had on trunk, but relying on different properties of the enums. * Once this is implemented, the following tests fail to compile: CHECK_VALID (true, int, true ? EF () : EF2 ()) This is because it expects the enums to be promoted to signed int, instead of unsigned int (which is the true underlying type). I propose to remove these tests altogether, because: - The comment nearby say they are not very important. - Comparing 2 enums of different type like that is strange, relies on integer promotions and thus hurts readability. As per comments in the related PR, we likely don't want this type of code in gdb code anyway, so there's no point in testing it. - Most importantly, this type of comparison will be ill-formed in C++26 for regular enums, so enum_flags does not need to emulate that. Since this is the only place where the warning was suppressed, remove also the corresponding macro in include/diagnostics.h. The change has been tested by running the entire gdb test suite (make check) and comparing the results (testsuite/gdb.sum) against trunk. No noticeable differences have been observed. Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=31331 Tested-by: Keith Seitz <keiths@redhat.com> Approved-By: Tom Tromey <tom@tromey.com>
2024-12-19x86-64: correct CODE_5 relocsJan Beulich1-6/+6
Two of them had their numbers swapped; luckily they aren't really in use just yet. Correct indentation as well while at it.
2024-12-13xcoff reading dynamic relocsAlan Modra1-3/+3
This adds a sanity check to relocation symbol indices, and tidies code a little. The patch does result in a couple of testsuite failures rs6000-aix7.2 +FAIL: TLS relocations (32-bit) rs6000-aix7.2 +FAIL: TLS relocations (64-bit) That seems reasonable to me, because prior to this patch l_symndx was being set to -1 and -2 for .tdata and .tbss symbols resulting in a buffer overflow when accessing the syms array. bfd/ * xcofflink.c (_bfd_xcoff_canonicalize_dynamic_reloc): Prevent symbol array overflow on invalid relocation symbol index. Tidy code for relocs against standard sections. (xcoff_create_ldrel): Remove cast. include/ * coff/xcoff.h (struct internal_ldrel): Make l_symndx uint32_t. Make l_rtype and l_rsecnm int16_t.
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+4
.cfi directives only support the use of register numbers and not register names or aliases. This commit adds support for 4 formats, for example: .cfi_offset r1, 8 .cfi_offset ra, 8 .cfi_offset $r1,8 .cfi_offset $ra,8 The above .cfi directives are equivalent and all represent dwarf register number 1. Display register aliases as specified in the psABI during disassembly.
2024-12-02aarch64: GCS feature check in GNU note properties for input objectsSrinath Parvathaneni1-0/+1
This patch adds support for Guarded Control Stack in AArch64 linker. This patch implements the following: 1) Defines GNU_PROPERTY_AARCH64_FEATURE_1_GCS bit for GCS in GNU_PROPERTY_AARCH64_FEATURE_1_AND macro. 2) Adds readelf support to read and print the GCS feature in GNU properties in AArch64. Displaying notes found in: .note.gnu.property [ ]+Owner[ ]+Data size[ ]+Description GNU 0x00000010 NT_GNU_PROPERTY_TYPE_0 Properties: AArch64 feature: GCS 3) Adds support for the "-z gcs" linker option and document all the values allowed with this option (-z gcs[=always|never|implicit]) where "-z gcs" is equivalent to "-z gcs=always". When '-z gcs' option is omitted from the command line, it defaults to "implicit" and relies on the GCS feature marking in GNU properties. 4) Adds support for the "-z gcs-report" linker option and document all the values allowed with this option (-z gcs-report[=none|warning|error]) where "-z gcs-report" is equivalent to "-z gcs-report=warning". When this option is omitted from the command line, it defaults to "warning". The ABI changes adding GNU_PROPERTY_AARCH64_FEATURE_1_GCS to the GNU property GNU_PROPERTY_AARCH64_FEATURE_1_AND is merged into main and can be found in [1]. [1] https://github.com/ARM-software/abi-aa/blob/main/sysvabi64/sysvabi64.rst Co-authored-by: Matthieu Longo <matthieu.longo@arm.com> Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com>
2024-11-28Sync include/dwarf.h with gcc up to commit c4073a3d154Alexandra Hájková1-0/+26
Approved-by: Kevin Buettner <kevinb@redhat.com>
generated by cgit v1.1 at 2025-07-02 01:23:27 +0000