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| author | Monk Chiang <monk.chiang@sifive.com> | 2025-01-17 09:53:00 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2025-01-17 12:34:45 +0800 |
| commit | b4681c2e8a46af1559990398bbc8f010d26312ca (patch) | |
| tree | 2654ae6fa5a28092e9add06565a152fddcd8edeb /include | |
| parent | 1d458f0843141734b73f3a895dee73626fd85cb3 (diff) | |
| download | binutils-b4681c2e8a46af1559990398bbc8f010d26312ca.zip binutils-b4681c2e8a46af1559990398bbc8f010d26312ca.tar.gz binutils-b4681c2e8a46af1559990398bbc8f010d26312ca.tar.bz2 | |
RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.
https://github.com/riscv/riscv-cfi/releases/tag/v1.0
This patch only support the CFI instructions and CSR in assembler.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 33 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 3 |
2 files changed, 36 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1696ac7..71ad7ff 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2353,6 +2353,24 @@ #define MASK_HSV_W 0xfe007fff #define MATCH_HSV_D 0x6e004073 #define MASK_HSV_D 0xfe007fff +/* Zicfiss instructions. */ +#define MATCH_SSPUSH 0xce004073 +#define MASK_SSPUSH 0xfe0fffff +#define MATCH_SSPOPCHK 0xcdc04073 +#define MASK_SSPOPCHK 0xfff07fff +#define MATCH_SSRDP 0xcdc04073 +#define MASK_SSRDP 0xfffff07f +#define MATCH_SSAMOSWAP_W 0x4800202f +#define MASK_SSAMOSWAP_W 0xf800707f +#define MATCH_SSAMOSWAP_D 0x4800302f +#define MASK_SSAMOSWAP_D 0xf800707f +#define MATCH_C_SSPUSH 0x6081 +#define MASK_C_SSPUSH 0xffff +#define MATCH_C_SSPOPCHK 0x6281 +#define MASK_C_SSPOPCHK 0xffff +/* Zicfilp instructions. */ +#define MATCH_LPAD 0x17 +#define MASK_LPAD 0xfff /* Zicbop hint instructions. */ #define MATCH_PREFETCH_I 0x6013 #define MASK_PREFETCH_I 0x1f07fff @@ -4203,6 +4221,8 @@ #define CSR_SCTRDEPTH 0x15f #define CSR_VSCTRCTL 0x24e #define CSR_MCTRCTL 0x34e +/* Zicfissp CSR addresses. */ +#define CSR_SSP 0x11 /* Unprivileged Floating-Point CSR addresses. */ #define CSR_FFLAGS 0x1 #define CSR_FRM 0x2 @@ -4892,6 +4912,17 @@ DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S) /* XVentanaCondOps instructions. */ DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC) DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN) + +/* Zicfiss instructions. */ +DECLARE_INSN(sspush, MATCH_SSPUSH, MASK_SSPUSH) +DECLARE_INSN(sspopchk, MATCH_SSPOPCHK, MASK_SSPOPCHK) +DECLARE_INSN(c_sspush, MATCH_C_SSPUSH, MASK_C_SSPUSH) +DECLARE_INSN(c_sspopchk, MATCH_C_SSPOPCHK, MASK_C_SSPOPCHK) +DECLARE_INSN(ssrdp, MATCH_SSRDP, MASK_SSRDP) +DECLARE_INSN(ssamoswap_w, MATCH_SSAMOSWAP_W, MASK_SSAMOSWAP_W) +DECLARE_INSN(ssamoswap_d, MATCH_SSAMOSWAP_D, MASK_SSAMOSWAP_D) +/* Zicfilp instructions. */ +DECLARE_INSN(lpad, MATCH_LPAD, MASK_LPAD) #endif /* DECLARE_INSN */ #ifdef DECLARE_CSR /* Unprivileged Counter/Timers CSRs. */ @@ -5318,6 +5349,8 @@ DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, P DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) +/* Zicfiss CSRs. */ +DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZICFISS, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE) /* Dropped CSRs. */ DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P10, PRIV_SPEC_CLASS_1P12) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index e7d2d78..6bcea63 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -515,6 +515,9 @@ enum riscv_insn_class INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_ZVKSED, INSN_CLASS_ZVKSH, + INSN_CLASS_ZICFISS, + INSN_CLASS_ZICFISS_AND_ZCMOP, + INSN_CLASS_ZICFILP, INSN_CLASS_ZCB, INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, |