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2026-02-05bpf: add may_goto instruction [PR32176]David Faust1-0/+4
The BPF "may_goto" instruction is a special sort of conditional jump where the condition is determined by the BPF runtime. That is, it is a no-op until the runtime decides otherwise. For normal asm syntax, the mnemonic "jcond" is chosen in keeping with the style of following the opcode definitions in the Linux kernel uapi BPF headers. This instruction is not currently emitted by GCC, but it can be inserted into BPF programs via macros defined in the Linux kernel. PR gas/32176 include/ * opcode/bpf.h (BPF_CODE_JCOND): New. (bpf_insn_id): Add BPF_INSN_JCOND. opcodes/ * bpf-opc.c: Add entry for BPF_INSN_JCOND. gas/testsuite/ * gas/bpf/bpf.exp: Run new dump tests. * gas/bpf/jcond-be-pseudoc.d: New. * gas/bpf/jcond-be.d: New. * gas/bpf/jcond-pseudoc.d: New. * gas/bpf/jcond-pseudoc.s: New. * gas/bpf/jcond.d: New. * gas/bpf/jcond.s: New.
2026-01-24aarch64: Add -march=armv9.7-a optionAlice Carlotti1-0/+7
2026-01-24aarch64: Enable TLBIP instructions with tlbid optionSrinath Parvathaneni1-0/+2
TLBI Domains feature changes TLBI and TLBIP system instructions. For all TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and TLBIP *E2OS* instructions that are currently dependent on FEAT_D128 (+d128), will also be available with FEAT_TLBID (+tlbid).
2026-01-24aarch64: Add support for FEAT_TLBID featureSrinath Parvathaneni1-0/+3
TLBI Domains feature changes TLBI and TLBIP system instructions. For the TLBI instruction with optional register argument <Rt> == 0b1111, with FEAT_TLBID enabled they are permitted to have an Rt value which is not 0b11111 and this is allowed for all the TLBI instructions with a <type> of ALLE1*, ALLE2*, VMALL*, VMALLS12* or VMALLWS2* and a <shareability> of IS or OS. This patch add support for FEAT_TLBID feature, which is enabled by new +tlbid option.
2026-01-16aarch64: Add support for FEAT_MTETCRichard Ball1-0/+2
This patch adds two new DC operations: *gbva *zgbva
2026-01-16aarch64: Add support for FEAT_CMHRichard Ball1-0/+3
This patch adds the new instructions from FEAT_CMH These new instructions are hints, STCPH and SHUH. SHUH can have an operand PH or no operand.
2026-01-16aarch64: Add support for MLBI system instructionsRichard Ball1-0/+2
This patch adds support for MLB invalidate (MLBI) instruction. Syntax: MLBI <mlbi_op>{, <Xt>} This instruction is an alias to "SYS #4, C7, C0, #<op2>{, <Xt>}" and MLBI being the preferred disassembly. The following list of MLBI operations are supported in this patch for the MLBI instructions enabled by "+mpamv2" * alle1 * vmalle1 * vpide1 * vpmge1
2026-01-16aarch64: Add FEAT_MPAMv2 system registersEzra Sitorus1-0/+2
2026-01-05aarch64: Add support for POE2 PLBI instructionSrinath Parvathaneni1-0/+2
This patch adds support for PLB invalidate operation (PLBI) instruction and the corresponding system registers as operand (<plbi_op>). Syntax: PLBI <plbi_op>{, <Xt>} This instruction is an alias to "SYS #<op1>, C10, <Cm>, #<op2>{, <Xt>}" and PLBI being the preferred disassembly. The following list of system registers are supported in this patch for the PLBI instructions enabled by "+poe2" flag and also the "nxs" variants of these system registers are enabled by "+poe2+xs" flag. * alle1 * alle1is * alle1os * alle2 * alle2is * alle2os * alle3 * alle3is * alle3os * aside1 * aside1is * aside1os * permae1 * permae1is * permae1os * perme1 * perme1is * perme1os * perme2 * perme2is * perme2os * perme3 * perme3is * perme3os * vmalle1 * vmalle1is * vmalle1os
2026-01-05aarch64: Add support for TEV instructionsSrinath Parvathaneni1-0/+3
This patch adds support for FEAT_TEV feature enabled by "+tev" flag along with support for following instructions. * TENTER * TEXIT TENTER instruction uses the existing AARCH64_OPND_NOT_BALANCED_17 operand to handle the not_balanced (NB) argument , where as a new operand AARCH64_OPND_NOT_BALANCED_10 is added to support the NB (not_balanced) argument in TEXIT instruction.
2026-01-05aarch64: Add support for POE2 instructionsSrinath Parvathaneni1-0/+3
This patch adds support for FEAT_S1POE2 feature enabled by "+poe2" flag along with support for following instructions. * TCHANGEB (immediate) * TCHANGEB (register) * TCHANGEF (immediate) * TCHANGEF (register) A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this patch to support the new optional argument "NB" (not_balanced) which is a 1-bit field in the encoding for all the above mentioned instructions. Co-authored-by: Matthew Malcomson <matthew.malcomson@arm.com>
2026-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
Avoid warnings about invalid escapes in etc/update-copyright.py by using raw strings, add BinutilsFilter to skip psql.rc and add "Kalray SA." as another copyright holder.
2025-12-29aarch64: Remove sme2_movaz instruction classAlice Carlotti1-1/+0
The behaviour of sme2_movaz was identical to sme_misc, so use that instead.
2025-12-27AArch64 v9.7 extensions: FEAT_SVE_B16MMSivan Shani1-0/+2
This patch includes: - Feature flag for FEAT_SVE_B16MM - Instruction: - BFMMLA (non-widening) BFloat16 matrix multiply-accumulate.
2025-12-27AArch64 v9.7 extensions: FEAT_F16MMSivan Shani1-0/+2
This patch includes: - Feature flag for FEAT_F16MM - Instructions: - FMMLA (non-widening) Half-precision matrix multiply-accumulate - FMMLA (non-widening) Floating-point matrix multiply-accumulate
2025-12-27AArch64: Add FEAT_F16F32MMSivan Shani1-0/+2
This patch includes: - The feature flag for the FEAT_F16F32MM feature. - Instruction FMMLA Half-precision matrix multiply-accumulate to single-precision.
2025-12-27AArch64: Add FEAT_F16F32DOT instructionsSivan Shani1-0/+2
This includes the instructions for the F16F32DOT feature: - FDOT half-precision to single-precision, by element - FDOT half-precision to single-precision, vector
2025-12-27AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.Sivan Shani1-0/+9
This patch includes: - Flags for the FEAT_SVE2p3 and FEAT_SME2p3 features. - Instructions: - ADDQP - ADDSUBP - FCVTZSN - FCVTZUN - LUTI6 16-bit - LUTI6 8-bit - SABAL - SCVTF - SCVTFLT - SDOT vectors - SDOT indexed - SQRSHRN - SQRSHRUN - SQSHRN - SQSHRUN - SUBP - UABAL - UCVTF - UCVTFLT - UDOT vectors - UDOT indexed - UQRSHRN - UQSHRN - LUTI6 vector - LUTI6 table, four registers - LUTI6 table, single, 8-bit In addition, new operands: - OPND_SME_Zmx2_INDEX_22: an operand represents a list of vector registers with an index. - OPND_SME_Zn7xN_UNTYPED: an operand represents an untyped list of vector registers.
2025-12-27aarch64: Add FEAT_MOPS_GO instructionsYury Khrustalev1-0/+2
Also add +mops-go feature flag and make the mops-go feature depend on the memtag and mops features.
2025-12-20LoongArch: Add disassembly support for ud ui5Lulu Cai1-0/+1
ud ui5, also known as amswap.w rd,$r1,rj(rd==rj), is displayed as "ud ui5" by default during disassembly. Alternatively, the original instruction can be printed using the objdump -M no-aliases. To implement this support, a format specifier "ru0:5,ru5:5" for ud is applied exclusively during disassembly. This specifier indicates that registers should be printed using their corresponding numeric values, and when the instruction is identified as ud, only a single parameter is displayed. binutils/ * testsuite/binutils-all/loongarch64/dis-amswap-ud-noaliases.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.d: New test. * testsuite/binutils-all/loongarch64/dis-amswap-ud.s: New test. gas/ * testsuite/gas/loongarch/macro_ud.d: Update test. include/ * opcode/loongarch.h: New macro. opcodes/ * loongarch-dis.c (get_loongarch_opcode_by_binfmt): Correct match `ud`. (dis_one_arg): Disassemble the `ud` parameter. * loongarch-opc.c: Add opcode for "ud" alias.
2025-12-15aarch64: Add support for new BTI <target> "r"Srinath Parvathaneni1-0/+1
This patch adds support for new BTI <target> "r" (instruction: bti r), which is an alias to "bti" (with no target), for both "bti" and "bti r" the preferred disassembly is "bti r". This "bti r" instruction is by default available from Armv8-A architecture. The HINT_OPD_F_NOPRINT macro has become redundant with these changes and has been removed.
2025-12-11aarch64: Add support for FEAT_LSCPRichard Ball1-0/+2
This patch adds the new instructions from FEAT_LSCP. These instructions are LDAP, LDAPP and STLP.
2025-12-10LoongArch: Add linker relaxation for got_pcadd_hi20 and got_pcadd_lo12mengqinggang1-0/+3
.L1: pcaddu12i $t0, %got_pcadd_hi20(a) -> pcaddu12i $t0, %pcadd_hi20(a) ld.w/d $t0, $t0, %got_pcadd_lo12(.L1) -> addi.w/d $t0, $t0, %pcadd_lo12(.L1)
2025-12-10LoongArch: Add support for tls type transition on LA32mengqinggang1-0/+1
desc -> le ie -> le desc -> ie For desc/ie -> le, need to change the symbol of le_lo12 to the symbol of [desc|ie]_pcadd_hi20.
2025-12-09LoongArch: Add support for the ud macro instructionLulu Cai1-0/+3
In the "ud ui5" macro, the value of ui5 must be in the range 0–31. It expands to "amswap.w $rd, $r1, $rj", where ui5 specifies the register number for $rd in the amswap.w instruction, and $rd == $rj. The test case have been adjusted to no longer report errors for illegal operands of the amswap.w instruction. gas/ * config/tc-loongarch.c (check_this_insn_before_appending): No longer check amswap.w. * testsuite/gas/loongarch/illegal-operand.l: Update. * testsuite/gas/loongarch/illegal-operand.s: Update. * testsuite/gas/loongarch/macro_ud.d: New test. * testsuite/gas/loongarch/macro_ud.s: New test. include/ * opcode/loongarch.h: Add new macro for amswap.w. opcodes/ * loongarch-opc.c: Add macro for ud.
2025-12-04aarch64: Improve comment for aarch64_opnd_info.sysreg.flagsAlice Carlotti1-1/+3
This field is used differently during assembly and disassembly. It would be nice if we could make this more consistent, but for now just extend the comment to explain what is going on.
2025-11-21RISC-V: Fixed opcodes for some bitmanip instructionstimurgol0071-0/+44
Currently some of the instructions in bitmanip extensions can not be obtained using DECLARE_INSN macros. I generated them using riscv-opcodes and added to other opcodes. Approved-By: Nelson Chu <nelson@rivosinc.com>
2025-10-10aarch64: Add support for FEAT_SSVE_BITPERMAlice Carlotti1-0/+4
2025-10-10aarch64: Add support for FEAT_SSVE_FEXPAAlice Carlotti1-0/+4
2025-10-10aarch64: Add support for FEAT_SME_MOP4Alice Carlotti1-2/+8
2025-10-10aarch64: Add support for FEAT_SME_TMOPAlice Carlotti1-0/+3
2025-10-10aarch64: Remove incorrect disassembly constraintAlice Carlotti1-1/+0
A check in print_insn_aarch64_word asserted that part of the encoding space couldn't contain any valid encodings, and then returned ERR_NYI ("Not Yet Implemented", perhaps?) for these values. However, some of the new FEAT_MOP4 instructions will trigger the assert. The check seems to be outdated, and is clearly no longer valid, so it can just be deleted. Additionally, there are no other assignments of ERR_NYI, so delete all remaining references to this error type.
2025-10-08aarch64, gas: Relax Armv9.6-A mandatory feature setAndre Vieira1-3/+1
Remove FPRCVT and SVE2p2 from the set of mandatory features for Armv9.6-A.
2025-10-06gas: aarch64: Add instructions for GICv5Saurabh Jha1-0/+6
Add new instructions from the Generic Interrupt Controller, GICv5, extension. These instructions are aliases to system instructions and are the following: * gic <operation>, <reg> * gicr <reg>, <operation> * gsb <operation>
2025-10-06gas: aarch64: Add flag for GICv5Saurabh Jha1-0/+2
Generic Interrupt Controller v5, GICv5, adds new system registers and system instructions. These are enabled with the +gcie flag, where gcie stands for GICv5 (Generic Interrupt Controller) CPU Interrupt Extension.
2025-09-23aarch64: Reorder feature bitsAlice Carlotti1-36/+23
Group the architecture version bits at the start of the enum, and add a comment explaining the purpose of AARCH64_FEATURE_V8A.
2025-09-23aarch64: Remove unused feature bitsAlice Carlotti1-69/+0
Many feature bits were unnecessarily added for features with no command line flags, and effectively acted as aliases of the architecture version bit they were linked to. The system register regating patch removed all uses of these feature bits, so we can just remove them.
2025-09-23aarch64: Remove F_ARCHEXT flagAlice Carlotti1-1/+1
The flag is unnecessary, because we can just unconditionally check the features field every time. Having the information duplicated in two separate fields makes it harder to maintain, particularly in the context of the upcoming regating patch. The reg_flags parameter of aarch64_sys_ins_reg_supported_p is now unused, so remove that as well.
2025-07-12aarch64: Add support for --march=armv9.6-aAlice Carlotti1-0/+10
2025-07-12aarch64: Refactor exclusion of reg names in immediatesAlice Carlotti1-1/+18
When parsing immediate values, register names should not be misinterpreted as symbols. However, for backwards compatibility we need to permit some newer register names within older instructions. The current mechanism for doing so depends on the list of explicit architecture requirements for the instructions, which is fragile and easy to forget, and grows increasingly messy as more architecture features are added. This patch add explicit flags to each opcode to indicate which set of register names is disallowed in each instance. These flags are mandatory for all opcodes with immediate operands, which ensures that the choice of disallowed names will always be deliberate and explicit. This patch should have no functional change.
2025-07-11aarch64: Support for FEAT_SVE_AES2Ezra Sitorus1-0/+9
FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption Standard and 128-bit destination element polynomial multiply long instructions, when the PE is not in Streaming SVE mode.
2025-07-11aarch64: Support for FEAT_LSUIEzra Sitorus1-0/+2
FEAT_LSUI introduces unprivileged variants of load and store instructions so that clearing PSTATE.PAN is never required in privileged software.
2025-07-11aarch64: Support for FEAT_PCDPHINTEzra Sitorus1-0/+3
FEAT_PCDPHINT - Producer-consumer data placement hints - is an optional ISA extension that provides hint instructions to indicate: - a store in the current execution thread is generating data at a specific location, which a thread of execution on one or more other observers is waiting on. - the thread of execution on the current PE will read a location that may not yet have been written with the value to be consumed. This extension introduces: - STSHH, a hint instruction, with operands (policies) keep and strm - PRFM *IR*, a new prefetch memory operand.
2025-07-10RISC-V: Clarify the imply rule of cNelson Chu1-4/+4
This also fix the imply result for .option rvc. Imply zcf when c and f and rv32 Imply zcd when c and d Imply zca when c Changed INSN_CLASS_C to INSN_CLASS_ZCA Changed INSN_CLASS_F_AND_C to INSN_CLASS_ZCF Changed INSN_CLASS_D_AND_C to INSN_CLASS_ZCD Changed INSN_CLASS_ZIHINTNTL_AND_C to INSN_CLASS_ZIHINTNTL_AND_ZCA
2025-07-09gas d30v_insn plus other non-const pointersAlan Modra1-2/+2
d30v has a bunch of casts that are only needed due to various types missing a const. Fix that.
2025-07-08aarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2Alice Carlotti1-1/+12
2025-06-25aarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
2025-06-24RISC-V: Support for unlabeled landing pad PLT generationKito Cheng1-0/+1
This patch adds support for generating unlabeled landing pad PLT entries for the RISC-V architecture. Unlabeled landing pad will place a LPAD instruction at the PLT entry and PLT header, also PLT header will have few changes due to the offset is different from the original one. Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
2025-06-19aarch64: Support for FEAT_LSFEEzra Sitorus1-2/+7
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
2025-06-19aarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
generated by cgit v1.1 at 2026-03-06 09:44:31 +0000