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7 daysaarch64: Add supports for FEAT_PoPS feature and DC instructions.Srinath Parvathaneni1-0/+2
This patch add support for FEAT_PoPS feature which can be enabled through +pops command line flag. This patch also adds support for following DC instructions and the spec can be found here [1]. 1. "dc cigdvaps" enabled on passing +memtag+pops command line flags. 2. "dc civaps" enabled on passing +pops command line flag. [1]: https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Instructions?lang=en
8 daysRISC-V: Support for unlabeled landing pad PLT generationKito Cheng1-0/+1
This patch adds support for generating unlabeled landing pad PLT entries for the RISC-V architecture. Unlabeled landing pad will place a LPAD instruction at the PLT entry and PLT header, also PLT header will have few changes due to the offset is different from the original one. Ref: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/417
13 daysaarch64: Support for FEAT_LSFEEzra Sitorus1-2/+7
FEAT_LSFE - Large System Float Extension - implements A64 base atomic floating-point in-memory instructions.
13 daysaarch64: Support for FEAT_SVE_F16F32MM, FEAT_F8F16M, FEAT_F8F32MMEzra Sitorus1-0/+6
FEAT_SVE_F16F32MM introduces the SVE half-precision floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F32MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to single-precision instruction. FEAT_F8F16MM introduces the Advanced SIMD 8-bit floating-point matrix multiply-accumulate to half-precision instruction.
13 daysaarch64: Support for FEAT_CMPBREzra Sitorus1-0/+5
FEAT_CMPBR - Compare and branch instructions. This patch adds these instructions: - CB<CC> (register) - CB<CC> (immediate) - CBH<CC> - CBB<CC> where CC is one of the following: - EQ - NE - GT - GE - LT - LE - HI - HS - LO - LS
13 daysaarch64: Add occmo flag for FEAT_OCCMOEzra Sitorus1-0/+2
FEAT_OCCMO support was introduced, but the feature flags were missing. This patch adds these flags, as well as splitting up the tests to test occmo vs occmo+memtag operands.
13 daysaarch64: Support for FEAT_SVE_BFSCALEEzra Sitorus1-0/+5
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE and BFMUL.
2025-06-12aarch64: Add support for FEAT_FPRCVTRichard Ball1-0/+4
FEAT_FPRCVT introduces new versions of previous instructions. The instructions are used to convert between floating points and Integers. These new versions take as operands SIMD&FP registers for both the source and destination register. FEAT_FPRCVT also enables the use of some existing AdvSIMD instructions in streaming mode. However, no changes are needed in gas to support this.
2025-06-11aarch64: Add definitions for missing architecture bitsYury Khrustalev1-4/+16
Complete macros for feature bits for v9.1-A, v9.2-A, v9.3-A, and v9.4-A.
2025-06-11kvx gcc-4.5 build fixesAlan Modra1-2/+2
More missing struct initialisers, for expressionS vars that in this case don't need to be initialised. Also an error: redefinition of typedef 'symbolS'. OK, so don't use a typedef.
2025-06-09aarch64: Increase the number of feature words to 3Richard Earnshaw1-1/+2
Now that most of the effort of updating the number of feature words is handled by macros, add an additional one, taking the number of supported features to 192.
2025-06-09aarch64: use macro trickery to automate feature array size replicationRichard Earnshaw1-36/+87
There are quite a few macros that need to be changed when we need to increase the number of words in the features data structure. With some macro trickery we can automate most of this so that a single macro needs to be updated. With C2X we could probably do even better by using recursion, but this is still a much better situation than we had previously. A static assertion is used to ensure that there is always enough space in the flags macro for the number of feature bits we need to support.
2025-06-09aarch64: Fix typos in opcode headersYury Khrustalev1-4/+4
2025-05-22RISC-V: Add support for Smcdeleg and Ssccfg extensions.Jiawei1-0/+4
This patch rebases the original patch from Nelson's implement[1]. Added new extension Smcdeleg and Ssccfg with a new CSR, scountinhibit.[2] Co-Authored-By: Nelson Chu <nelson@rivosinc.com> Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn> [1] https://patchwork.sourceware.org/project/binutils/patch/20240620045359.47513-1-nelson@rivosinc.com/ [2] https://github.com/riscvarchive/riscv-smcdeleg-ssccfg/releases/tag/v1.0.0 bfd/ChangeLog: * elfxx-riscv.c: New extensions. gas/ChangeLog: * NEWS: Mention new extensions. * config/tc-riscv.c (enum riscv_csr_class): New CSR class. (riscv_csr_address): Add support for Ssccfg. * testsuite/gas/riscv/csr-version-1p10.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.d: New test for Ssccfg CSR. * testsuite/gas/riscv/csr-version-1p13.l: New warning for Ssccfg CSR. * testsuite/gas/riscv/csr.s: New Ssccfg CSR. * testsuite/gas/riscv/imply.d: New imply check. * testsuite/gas/riscv/imply.s: New implies. * testsuite/gas/riscv/march-help.l: New helping info. include/ChangeLog: * opcode/riscv-opc.h (CSR_SCOUNTINHIBIT): New CSR address. (DECLARE_CSR): Add Ssccfg CSR.
2025-05-16RISC-V: Add zilsd & zclsd supportdysun1-0/+2
Ref: https://github.com/riscv/riscv-zilsd/blob/main/zilsd.adoc Signed-off-by: dysun <sundongya@nucleisys.com> Co-developed-by: LIU Xu <liuxu@nucleisys.com> Co-developed-by: ZHAO Fujin <zhaofujin@nucleisys.com>
2025-05-09aarch64: Eliminate AARCH64_OPND_SVE_ADDR_RAlice Carlotti1-6/+10
Adjust parsing for AARCH64_OPND_SVE_ADDR_RR{_LSL*} operands to accept implicit XZR offsets. Add new AARCH64_OPND_SVE_ADDR_RM{_LSL*} operands to support instructions where an XZR offset is allowed but must be specified explicitly. This allows the removal of the duplicate opcode table entries using AARCH64_OPND_SVE_ADDR_R.
2025-05-09RISC-V: Add Privileged Architecture 1.13 CSRs.Jiawei1-0/+4
This patch support RISC-V Privileged Architecture 1.13 CSRs 'medelegh' and 'hedelegh'. More details between 1.12 and 1.13 see [1]. [1] https://github.com/riscv/riscv-isa-manual/blob/main/src/priv-preface.adoc Version log: Remove gas/po changes. bfd/ChangeLog: * cpu-riscv.c: New option. * cpu-riscv.h (enum riscv_spec_class): Ditto. binutils/ChangeLog: * doc/binutils.texi: New option. gas/ChangeLog: * NEWS: Add priv-1.13 support. * config/tc-riscv.c: New option. * configure: Ditto. * configure.ac: Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: New warning. * testsuite/gas/riscv/csr-version-1p11.d: New CSR. * testsuite/gas/riscv/csr-version-1p11.l: New warning. * testsuite/gas/riscv/csr-version-1p12.d: New CSR. * testsuite/gas/riscv/csr-version-1p12.l: New warning. * testsuite/gas/riscv/csr.s: New CSR. * testsuite/gas/riscv/attribute-15.d: New test. * testsuite/gas/riscv/attribute-16.d: New test. * testsuite/gas/riscv/csr-version-1p13.d: New test. * testsuite/gas/riscv/csr-version-1p13.l: New test. include/ChangeLog: * opcode/riscv-opc.h (CSR_MEDELEGH): New CSR. (CSR_HEDELEGH): Ditto. (DECLARE_CSR): Ditto.
2025-05-09RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslspChao-ying Fu2-0/+69
Spec: https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf Added MIPS vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp with verison 1.0. Passed binutils testsuites of targets elf32/elf64/linux32/linux64. Signed-off-by: Jovan Dmitrović <jovan.dmitrovic@htecgroup.com> Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
2025-03-26RISC-V: add Smrnmi 1.0 instruction supportJerry Zhang Jian2-0/+6
Add instruction `mnret' support Ref: https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi bfd/ChangeLog: * elfxx-riscv.c: Add new Smrnmi instruction class handling gas/ChangeLog: * testsuite/gas/riscv/smrnmi.s: New test for mnret * testsuite/gas/riscv/rmrnmi.d: Likewise include/ChangeLog: * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET * opcode/riscv.h: Add new instruction class opcodes/ChangeLog: * riscv-opc.c: Add `mnret' instruction Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
2025-03-18RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1]Jin Ma2-0/+16
T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the additional extension "XTheadVdot" based on the "V" extension, and it provides four 8-bit multiply and add with 32-bit instructions for the "v" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([2]). Co-Authored-By: Lifang Xia <lifang_xia@linux.alibaba.com> [1] https://github.com/XUANTIE-RV/thead-extension-spec/tree/master/xtheadvdot [2] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add support for "XTheadVdot" extension. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: Likewise. * testsuite/gas/riscv/march-help.l: Likewise. * testsuite/gas/riscv/x-thead-vdot.d: New test. * testsuite/gas/riscv/x-thead-vdot.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VMAQA_VV): New. * opcode/riscv.h (enum riscv_insn_class): Add insn class for XTheadVdot. opcodes/ChangeLog: * riscv-opc.c: Likewise.
2025-03-03RISC-V: Support ssqosid extension with version 1.0.Kito Cheng1-0/+4
It only add one new CSR: `srmcfg`. Ref: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
2025-01-17aarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti1-2/+8
Many FEAT_SVE2p1 instructions need to be enabled by either of two different features (one for streaming mode, and one for non-streaming mode). This patch adds correct gating conditions for these instructions. There were also a few sve2p1 instructions missing altogether, so add those as well. The testsuite is modified to check for all alternative enablement conditions. In many cases this is done by adding an alternative assembler commands to existing test files. For some SME/SME2 tests, only some of the instructions are enabled by +sve2p1, so these are copied into a separate test. For original SVE2p1 tests, the non-SME2p1 instructions have been moved to a separate test file. There are also new tests for the newly added instructions. These include a couple of fixme comments relating to bad error reporting, which should be investigated later.
2025-01-17RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang2-0/+36
https://github.com/riscv/riscv-cfi/releases/tag/v1.0 This patch only support the CFI instructions and CSR in assembler.
2025-01-17RISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu2-3/+18
https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0 The privileged spec v1.10 already removed the sfence.vm instruction, and the encoding of sfence.vm instruction is overlapped with the sctrclr instruction of ssctr/smctr. But since the privileged spec v1.10 already removed the sfence.vm, and we no longer support the privileged spec v1.9.1 for now, we had to remove the sfence.vm. bfd/ * elfxx-riscv.c (riscv_implicit_subsets): Imply zicsr for ssctr/smctr. (riscv_supported_std_s_ext): Added ssctr/smctr with version 1.0. (riscv_multi_subset_supports): Handle INSN_CLASS for ssctr/smctr. (riscv_multi_subset_supports_ext): Likewise. gas/ * config/tc-riscv.c (enum riscv_csr_class, riscv_csr_address): Added and handle CSR_CLASS_SSCTR and CSR_CLASS_SMCTR. (riscv_is_priv_insn): Removed SFENCE_VM check. * testsuite/gas/riscv/attribute-14e.d: Removed since sfence.vm is no longer supported since privileged spec v1.10. * testsuite/gas/riscv/attribute-14.s: Likewise. * testsuite/gas/riscv/csr-version-1p10.d: Updated for ssctr/smctr CSRs. * testsuite/gas/riscv/csr-version-1p10.l: Likewise. * testsuite/gas/riscv/csr-version-1p11.d: Likewise. * testsuite/gas/riscv/csr-version-1p11.l: Likewise. * testsuite/gas/riscv/csr-version-1p12.d: Likewise. * testsuite/gas/riscv/csr-version-1p12.l: Likewise. * testsuite/gas/riscv/csr.s: Likewise. * testsuite/gas/riscv/csr-dw-regnums.d: Likewise. * testsuite/gas/riscv/csr-dw-regnums.s: Likewise. * testsuite/gas/riscv/march-help.l: Updated for ssctr/smctr. * testsuite/gas/riscv/smctr-ssctr.d: New testcase for sctr instruction. * testsuite/gas/riscv/smctr-ssctr.s: Likewise. include/ * opcode/riscv-opc.h: Added encoding macro for sctrclr, but removed encoding macro for sfence.vm since encoding conflict. Added CSR numbers for ssctr/smctr CSRs. * opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_SMCTR_OR_SSCTR for sctrclr. opcodes/ * riscv-opc.c (riscv_opcodes): Added sctrclr, but removed sfence.vm since encoding conflict.
2025-01-10aarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for SME ZA-targeting non-widening BFloat16 instructions, under tick FEAT_SME_B16B16 and command line flag "+sme-b16b16". FEAT_SME_B16B16 implements FEAT_SME2 and FEAT_SVE_B16B16, in accordance with that "+sme-b16b16" enables "+sme2" and "+sve-b16b16". Also the test files related to FEAT_SME_B16B16 are prefixed with sme-b16b16*. eg: sme-b16b16-1.s, sme-b16b16-1.d. The spec for this feature and instructions is availabe here [1]: [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
2025-01-10aarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-2/+2
In the current code, SVE2 Bfloat16 instructions are implemented with tick FEAT_B16B16 and command line flag "+b16b16" and this feature was suspended due to incomplete support. In the new spec available here[1], FEAT_B16B16 is replaced with FEAT_SVE_B16B16 and command line flag "+b16b16" is replace with "sve-b16b16". Also the test files related to FEAT_SVE_B16B16 are prefixed with sve-b16b16*. eg: sve-b16b16-sve2-1.s, sve-b16b16-sve2-1.d. This patch supports the SVE Z-targeting non-widening BFloat16 instructions with command line flag "+sve-b16b16+sve2". [1]: https://developer.arm.com/documentation/ddi0602/2024-06/SVE-Instructions?lang=en
2025-01-10aarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti1-1/+1
Rename to AARCH64_OPND_SME_ZT0_INDEX_MUL_VL.
2025-01-10aarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti1-1/+0
2025-01-10aarch64: Add support for FEAT_SME_F16F16 feature.Srinath Parvathaneni1-0/+2
This patch adds support for FEAT_SME_F16F16 feature (Non-widening half-precision FP16 to FP16 arithmetic for SME2), which is enabled using command line flags +sme-f16f16 to -march (which enables both FEAT_SME2 and FEAT_SME_F16F16). There are couple of instructions (fadd and fsub variants) which should be allowed by the assembler on either passing +sme-f16f16 or +sme-f8f16. Those instructions are already supported in the current assembler, this patch adds tests for those instructions as well.
2025-01-06RISC-V: Eliminate redundant instruction macroXiao Zeng1-1/+0
include/ChangeLog: * opcode/riscv.h: Eliminate redundant instruction macro M_j. Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>
2025-01-01Update year range in copyright notice of binutils filesAlan Modra69-69/+69
2024-12-27LoongArch: Fix resolution of undefined weak hidden/protected symbolsXi Ruoyao1-0/+2
An undefined weak hidden/protect symbol should be resolved to runtime address 0, but we were actually resolving it to link-time address 0. So in PIE or DSO the runtime address would be incorrect. Fix the issue by rewriting pcalau12i to lu12i.w, and pcaddi to addi.w. The latter does not always work because the immediate field of addi.w is narrower, report an error in the case the addend is too large. Signed-off-by: Xi Ruoyao <xry111@xry111.site>
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+4
.cfi directives only support the use of register numbers and not register names or aliases. This commit adds support for 4 formats, for example: .cfi_offset r1, 8 .cfi_offset ra, 8 .cfi_offset $r1,8 .cfi_offset $ra,8 The above .cfi directives are equivalent and all represent dwarf register number 1. Display register aliases as specified in the psABI during disassembly.
2024-11-26nios2: Remove binutils support for Nios II target.Sandra Loosemore3-1790/+0
The Nios II architecture has been EOL'ed by the vendor. This patch removes all binutils, bfd, gas, binutils, and opcodes support for this target with the exception of the readelf utility. (The ELF EM_* number remains valid and the relocation definitions from the Nios II ABI will never change in future, so retaining the readelf support seems consistent with its purpose as a utility that tries to parse the headers in any ELF file provided as an argument regardless of target.)
2024-11-22RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and ↵Nelson Chu2-0/+25
xsfvfnrclipxfqf Those SiFive extensions have been published on the web for a while, and we plan to implement intrinsics in GCC for those instructions soon. NOTE: The original patch was written by Nelson when he was still working at SiFive, and Kito rebased it to the trunk. Therefore, I kept the author as Nelson with his SiFive email. Document links: xsfvqmaccdod: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvqmaccqoq: https://www.sifive.com/document-file/sifive-int8-matrix-multiplication-extensions-specification xsfvfnrclipxfqf: https://www.sifive.com/document-file/fp32-to-int8-ranged-clip-instructions Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2024-11-20RISC-V: Add Zcmt instructions and csr.Jiawei2-0/+17
This patch supports Zcmt[1] instruction 'cm.jt' and 'cm.jalt'. Add new CSR jvt for tablejump using. Since 'cm.jt' and 'cm.jalt' have the same instructiong encoding, use 'match_cm_jt' and 'match_cm_jalt' check the 'zcmt_index' field to distinguish them. [1] https://github.com/riscvarchive/riscv-code-size-reduction/releases Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * config/tc-riscv.c (enum riscv_csr_class): New CSR. (riscv_csr_address): Ditto. (validate_riscv_insn): New operand. (riscv_ip): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New CSR. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. * testsuite/gas/riscv/zcmt-fail.d: New test. * testsuite/gas/riscv/zcmt-fail.l: New test. * testsuite/gas/riscv/zcmt-fail.s: New test. * testsuite/gas/riscv/zcmt.d: New test. * testsuite/gas/riscv/zcmt.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_JT): New opcode. (MASK_CM_JT): New mask. (MATCH_CM_JALT): New opcode. (MASK_CM_JALT): New mask. (CSR_JVT): New CSR. (DECLARE_INSN): New declaration. (DECLARE_CSR): Ditto. * opcode/riscv.h (EXTRACT_ZCMT_INDEX): New marco. (ENCODE_ZCMT_INDEX): Ditto. (enum riscv_insn_class): New class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): New operand. * riscv-opc.c (match_cm_jt): New function. (match_cm_jalt): Ditto.
2024-11-08aarch64: improve debuggability on array of enumMatthieu Longo1-3/+3
The current space optmization on enum aarch64_opn_qualifier forced its encoding using an unsigned char. This "hard-coded" optimization has the bad consequence of making the array of such enums being completely unreadable when debugging with GDB because the enum type is lost along the way. Keeping this space optimization, and the enum type as well, is possible when the declaration of the enum is tagged with attribute((packed)). attribute((packed)) is a GNU extension, and is wrapped in the macro ATTRIBUTE_PACKED (defined in ansidecl.h), and should be used instead.
2024-11-08aarch64: change returned type to bool to match semantic of functionsMatthieu Longo1-1/+1
2024-11-08aarch64: make comment clearer about the locationMatthieu Longo1-1/+2
The enum aarch64_opnd_qualifiers in include/opcode/aarch64.h needs to stay in sync with the array of struct operand_qualifier_data which defines various properties for the different type of operands. For instance, for: - registers: the size of the register, the number of elements. - immediates: lower and upper bits to determine the range of values.
2024-11-08arm, objdump: Make objdump use bfd's machine detection to drive disassemblyAndre Vieira1-2/+2
For any arm elf target, disable an old piece of code that forced disassembly to disassemble for 'unknown architecture' which once upon a time meant it would disassemble ANY arm instruction. This is no longer true with the addition of Armv8.1-M Mainline, as there are conflicting encodings for different thumb instructions. BFD however can detect what architecture the object file was assembled for using information in the notes section. So if available, we use that, otherwise we default to the old 'unknown' behaviour. With the changes above code, a mode changing 'bx lr' assembled for armv4 with the option --fix-v4bx will result in an object file that is recognized by bfd as one for the armv4 architecture. The disassembler now disassembles this encoding as a BX even for Armv4 architectures, but warns the user when disassembling for Armv4 that this instruction is only valid from Armv4T onwards. Remove the unused and wrongfully defined ARM_ARCH_V8A_CRC, and define and use a ARM_ARCH_V8R_CRC to make sure instructions enabled by -march=armv8-r+crc are disassembled correctly. Patch up some of the tests cases, see a brief explanation for each below. inst.d: This test checks the assembly & disassembly of basic instructions in armv3m. I changed the expected behaviour for teqp, cmnp cmpp and testp instructions to properly print p when disassembling, whereas before, in the 'unknown' case it would disassemble these as UNPREDICTABLE as they were changed in later architectures. nops.d: Was missing an -march, added one to make sure we were testing the right behavior of NOP<c> instructions. unpredictable.d: Was missing an -march, added armv6 as that reproduced the behaviour being tested.
2024-10-10s390: Add arch15 instructionsAndreas Krebbel1-0/+1
opcodes/ * s390-mkopc.c (main) Accept arch15 as CPU string. * s390-opc.txt: Add arch15 instructions. include/ * opcode/s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_ARCH15. gas/ * config/tc-s390.c (s390_parse_cpu): New entry for arch15. * doc/c-s390.texi: Document arch15 march option. * doc/as.texi: Likewise. * testsuite/gas/s390/s390.exp: Run the arch15 related tests. * testsuite/gas/s390/zarch-arch15.d: Tests for arch15 instructions. * testsuite/gas/s390/zarch-arch15.s: Likewise. Signed-off-by: Andreas Krebbel <krebbel@linux.ibm.com> Reviewed-by: Jens Remus <jremus@linux.ibm.com>
2024-09-25RISC-V: Add Smrnmi extension csrs.Jiawei1-0/+10
This patch support Smrnmi extension[1], The csrs address can be find in[2]. [1] https://github.com/riscv/riscv-isa-manual/commit/35eb3948bf0b87c83fab5a7238bd68b6211faf62 [2] https://github.com/riscv/riscv-isa-manual/blob/smrnmi-1.0/src/priv-csrs.adoc bfd/ChangeLog: * elfxx-riscv.c: New extension. gas/ChangeLog: * NEWS: Add Smrnmi extension support. * config/tc-riscv.c (enum riscv_csr_class): New extension class. (riscv_csr_address): Ditto. * testsuite/gas/riscv/csr-version-1p10.d: New csrs. * testsuite/gas/riscv/csr-version-1p10.l: Ditto. * testsuite/gas/riscv/csr-version-1p11.d: Ditto. * testsuite/gas/riscv/csr-version-1p11.l: Ditto. * testsuite/gas/riscv/csr-version-1p12.d: Ditto. * testsuite/gas/riscv/csr-version-1p12.l: Ditto. * testsuite/gas/riscv/csr.s: Ditto. * testsuite/gas/riscv/march-help.l: New extension. include/ChangeLog: * opcode/riscv-opc.h (CSR_MNSCRATCH): New csr. (CSR_MNEPC): Ditto. (CSR_MNCAUSE): Ditto. (CSR_MNSTATUS): Ditto. (DECLARE_CSR): New csr declarations.
2024-09-15MIPS/opcodes: Rework documentation for instruction argsMaciej W. Rozycki1-400/+402
Rewrite the inline documentation for the characters used in the `args' member of `struct mips_opcode' to make it consistent in terms of style and formatting. Discard references to inexistent macros.
2024-09-12s390: Simplify (dis)assembly of insn operands with const bitsJens Remus1-4/+0
Simplify assembly and disassembly of extended mnemonics with operands with constant ORed bits: Their instruction template already contains the respective constant operand bits, as they are significant to distinguish the extended from their base mnemonic. Operands are ORed into the instruction template. Therefore it is not necessary to OR the constant bits into the operand value during assembly in s390_insert_operand. Additionally the constant operand bits from the instruction template can be used to mask them from the operand value during disassembly in s390_print_insn_with_opcode. For now do so for non-length unsigned integer operands only. The separate instruction formats need to be retained, as their masks differ, which is relevant during disassembly to distinguish the base and extended mnemonics from each other. This affects the following extended mnemonics: - vfaebs, vfaehs, vfaefs - vfaezb, vfaezh, vfaezf - vfaezbs, vfaezhs, vfaezfs - vstrcbs, vstrchs, vstrcfs - vstrczb, vstrczh, vstrczf - vstrczbs, vstrczhs, vstrczfs - wcefb, wcdgb - wcelfb, wcdlgb - wcfeb, wcgdb - wclfeb, wclgdb - wfisb, wfidb, wfixb - wledb, wflrd, wflrx include/ * opcode/s390.h (S390_OPERAND_OR1, S390_OPERAND_OR2, S390_OPERAND_OR8): Remove. opcodes/ * s390-opc.c (U4_OR1_24, U4_OR2_24, U4_OR8_28): Remove. (INSTR_VRR_VVV0U1, INSTR_VRR_VVV0U2, INSTR_VRR_VVV0U3): Define as INSTR_VRR_VVV0U0 while retaining respective insn fmt mask. (INSTR_VRR_VV0UU8): Define as INSTR_VRR_VV0UU while retaining respective insn fmt mask. (INSTR_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB3): Define as INSTR_VRR_VVVU0VB while retaining respective insn fmt mask. * s390-dis.c (s390_print_insn_with_opcode): Mask constant operand bits set in insn template of non-length unsigned integer operands. gas/ * config/tc-s390.c (s390_insert_operand): Do not OR constant operand value bits. Signed-off-by: Jens Remus <jremus@linux.ibm.com>
2024-09-07Add macros to get opcode of instructions approriatelyXin Wang1-5/+65
LoongArch: Add macros to get opcode and register of instructions appropriately Currently, we get opcode of an instruction by manipulate the binary with it's mask, it's a bit of a pain. Now a macro is defined to do this and a macro to get the RD and RJ registers which is applicable to most instructions of LoongArch are added.
2024-09-03RISC-V: Add support for XCVsimd extension in CV32E40PMary Bennett2-0/+452
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvsimd` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): Add custom operands. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVsimd as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvsimd. * testsuite/gas/riscv/x-cv-simd.d: New test. * testsuite/gas/riscv/x-cv-simd.s: New test. * testsuite/gas/riscv/x-cv-simd-fail.d: New test. * testsuite/gas/riscv/x-cv-simd-fail.l: New test. * testsuite/gas/riscv/x-cv-simd-fail.s: New test. include/ChangeLog: * opcode/riscv-opc.h: Add corresponding MATCH and MASK macros for XCVsimd. * opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVsimd. (enum riscv_insn_class): Add the XCVsimd instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands. * riscv-opc.c: Add XCVsimd instructions.
2024-08-27RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions.Jiawei2-0/+18
This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com> Co-Authored by: Simon Cook <simon.cook@embecosm.com> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn> gas/ChangeLog: PR 32036 * NEWS: Updated. * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: PR 32036 * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: PR 32036 * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function.
2024-08-06RISC-V: Add support for XCvBitmanip extension in CV32E40PMary Bennett2-2/+44
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html Contributors: Mary Bennett <mary.bennett682@gmail.com> Nandni Jamnadas <nandni.jamnadas@embecosm.com> Pietra Ferreira <pietra.ferreira@embecosm.com> Charlie Keaney Jessica Mills Craig Blackmore <craig.blackmore@embecosm.com> Simon Cook <simon.cook@embecosm.com> Jeremy Bennett <jeremy.bennett@embecosm.com> Helene Chelin <helene.chelin@embecosm.com> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add `xcvbitmanip` instruction class. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add custom operands `Xc6` and `Xc7`. (riscv_ip): Likewise. * doc/c-riscv.texi: Note XCVbitmanip as an additional ISA extension for CORE-V. * testsuite/gas/riscv/march-help.l: Add xcvbitmanip. * testsuite/gas/riscv/x-cv-bitmanip-fail.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.l: New Test. * testsuite/gas/riscv/x-cv-bitmanip-fail.s: New Test. * testsuite/gas/riscv/x-cv-bitmanip.d: New Test. * testsuite/gas/riscv/x-cv-bitmanip.s: New Test. include/opcode/ChangeLog: * riscv-opc.h: Add corresponding MATCH and MASK macros for XCVbitmanip. * riscv.h: Add corresponding EXTRACT and ENCODE macros for XCVbitmanip. (enum riscv_insn_class): Add the XCVbitmanip instruction class. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Add custom operands `Xc6` and `Xc7`. * riscv-opc.c: Add XCvBitmanip instructions.
2024-08-06RISC-V: Add support for Zcmop extensionXiao Zeng2-0/+27
This implements the Zcmop (Compressed Zimop) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> The Zcmop extension requires the Zca extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zcmop.d: New test. * testsuite/gas/riscv/zcmop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop. (MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7, MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define. (MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7, MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zcmop instructions.
2024-08-06RISC-V: Add support for Zimop extensionXiao Zeng2-0/+123
This implements the Zimop (May-Be-Operations) extension, as of version 1.0. View detailed information in: <https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc> bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Handle Zimop (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Updated. * testsuite/gas/riscv/march-help.l: Ditto. * testsuite/gas/riscv/zimop.d: New test. * testsuite/gas/riscv/zimop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zimop. (MATCH_MOP_R_0, MATCH_MOP_R_1, MATCH_MOP_R_2, MATCH_MOP_R_3, MATCH_MOP_R_4, MATCH_MOP_R_5, MATCH_MOP_R_6, MATCH_MOP_R_7, MATCH_MOP_R_8, MATCH_MOP_R_9, MATCH_MOP_R_10, MATCH_MOP_R_11, MATCH_MOP_R_12, MATCH_MOP_R_13, MATCH_MOP_R_14, MATCH_MOP_R_15, MATCH_MOP_R_16, MATCH_MOP_R_17, MATCH_MOP_R_18, MATCH_MOP_R_19, MATCH_MOP_R_20, MATCH_MOP_R_21, MATCH_MOP_R_22, MATCH_MOP_R_23, MATCH_MOP_R_24, MATCH_MOP_R_25, MATCH_MOP_R_26, MATCH_MOP_R_27, MATCH_MOP_R_28, MATCH_MOP_R_29, MATCH_MOP_R_30, MATCH_MOP_R_31, MATCH_MOP_RR_0, MATCH_MOP_RR_1, MATCH_MOP_RR_2, MATCH_MOP_RR_3, MATCH_MOP_RR_4, MATCH_MOP_RR_5, MATCH_MOP_RR_6, MATCH_MOP_RR_7): Define. (MASK_MOP_R_0, MASK_MOP_R_1, MASK_MOP_R_2, MASK_MOP_R_3, MASK_MOP_R_4, MASK_MOP_R_5, MASK_MOP_R_6, MASK_MOP_R_7, MASK_MOP_R_8, MASK_MOP_R_9, MASK_MOP_R_10, MASK_MOP_R_11, MASK_MOP_R_12, MASK_MOP_R_13, MASK_MOP_R_14, MASK_MOP_R_15, MASK_MOP_R_16, MASK_MOP_R_17, MASK_MOP_R_18, MASK_MOP_R_19, MASK_MOP_R_20, MASK_MOP_R_21, MASK_MOP_R_22, MASK_MOP_R_23, MASK_MOP_R_24, MASK_MOP_R_25, MASK_MOP_R_26, MASK_MOP_R_27, MASK_MOP_R_28, MASK_MOP_R_29, MASK_MOP_R_30, MASK_MOP_R_31, MASK_MOP_RR_0, MASK_MOP_RR_1, MASK_MOP_RR_2, MASK_MOP_RR_3, MASK_MOP_RR_4, MASK_MOP_RR_5, MASK_MOP_RR_6, MASK_MOP_RR_7): Ditto. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZIMOP. opcodes/ChangeLog: * riscv-opc.c: Add Zimop instructions.
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