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AgeCommit message (Expand)AuthorFilesLines
2018-07-22x86: Determine vector length from the last vector operandH.J. Lu2-10/+31
2018-07-21gas/config/tc-i386.c: Break long lineH.J. Lu2-4/+11
2018-07-20x86: Rename match_reg_size to match_operand_sizeH.J. Lu2-11/+22
2018-07-20MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3aChenghua Xu14-339/+460
2018-07-20Specify architecture for SPARC gas testsRainer Orth2-23/+62
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich2-1/+26
2018-07-19x86: fold various AVX512BW templatesJan Beulich2-2/+6
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich3-4/+53
2018-07-18MIPS/GAS/testsuite: Correct whitespace issues with Loongson testsMaciej W. Rozycki12-294/+296
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu3-0/+16
2018-07-16x86: fix operand size checkingJan Beulich4-86/+123
2018-07-13Add a test that relocs are correctly generated for missing build notes.Nick Clifton4-0/+30
2018-07-13Allow bit-patterns in the immediate field of ARM neon mov instructions.Nick Clifton4-4/+33
2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton3-363/+374
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina4-0/+205
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das8-6/+29
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich2-7/+8
2018-07-11x86: simplify legacy prefix emissionJan Beulich2-10/+9
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich7-0/+26
2018-07-11x86: fix "REP RET" with -madd-bnd-prefixJan Beulich8-8/+45
2018-07-09 * testsuite/nds32/ji-jr.d: Fix name tag.Jeff Law2-1/+5
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina3-0/+33
2018-07-06Fix the relocs created to adjust notes created by the assembler.Nick Clifton2-3/+8
2018-07-05Updated Russian, Bulgarian, and Brazilian Portuguese translations for various...Nick Clifton2-2992/+3079
2018-07-02microMIPS/GAS: Handle several percent-ops with macrosMaciej W. Rozycki8-1/+692
2018-07-02microMIPS/BFD: Add missing NewABI TLS and miscellaneous relocationsMaciej W. Rozycki4-0/+284
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme2-42/+47
2018-07-02Fix use of "command line X" in binutils docThomas Preud'homme34-239/+275
2018-06-29RISC-V: Add gas support for "fp" register.Jim Wilson2-0/+7
2018-06-29[Patch AArch64] Warn on unpredictable stlxrb , stlxrh and stlxr cases.Ramana Radhakrishnan4-0/+44
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina7-40638/+64846
2018-06-27gas object file locationsAlan Modra3-112/+117
2018-06-26Updated translations.Nick Clifton2-2993/+3074
2018-06-26Fix the MSP430 assembler's parsing of register names.Nick Clifton3-133/+150
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton3-2957/+2616
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton2-0/+7
2018-06-22Correct negs aliasing on AArch64.Tamar Christina3-0/+180
2018-06-21Regen doc/Makefile.inAlan Modra3-4/+9
2018-06-20Change the ARM assembler's ADR and ADRl pseudo-ops so that they will only set...Nick Clifton7-6/+44
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber9-0/+103
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi10-2532/+2217
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker15-0/+125
2018-06-14MIPS: Add CRC ASE support (ChangeLog)Maciej W. Rozycki1-0/+1
2018-06-13MIPS: Add CRC ASE supportScott Egerton20-0/+232
2018-06-11MIPS/GAS: Correct `-O0' and `-O' option help, add `-O1' and `-O2'Maciej W. Rozycki2-2/+8
2018-06-08[arm][gas] Add support for Arm Cortex-A76kyrtka013-0/+9
2018-06-08[AArch64][gas] Add support for Arm Cortex-A76kyrtka013-0/+9
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu5-1/+101
2018-06-07Fix AArch64 unintialized variable which can cause diagnostic failures.Tamar Christina2-0/+8
2018-06-06Update the AArch64 assembler to note that the Qualcomm Saphira cpu supports A...Sameera Deshpande2-1/+6
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