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authorJan Beulich <jbeulich@novell.com>2018-07-19 08:29:35 +0200
committerJan Beulich <jbeulich@suse.com>2018-07-19 08:29:35 +0200
commit7091c612013ed63fedabc26b1662c87071e41fd6 (patch)
tree0e5ae7799562d136a06050ba4cdae2b05af23045 /gas
parentc30be56ebf7989e36f5c7d4a703cb00f7d4ca2ab (diff)
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x86: fold various AVX512VL templates into their AVX512F counterparts
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-i386.c45
-rw-r--r--gas/testsuite/gas/i386/noavx512-2.l4
3 files changed, 53 insertions, 4 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9cda0a6..42f4c12 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (is_evex_encoding): Also check disp8memshift.
+ (optimize_encoding): Also cover templates without cpuavx512vl
+ allowing for zmmword and having a ymmword actual.
+ (check_VecOperands): Handle DISP8_SHIFT_VL.
+ * testsuite/gas/i386/noavx512-2.l: Adjust expectations.
+
2018-07-18 Maciej W. Rozycki <macro@mips.com>
* testsuite/gas/mips/loongson-2e.d: Correct whitespace issues.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fd2e817..d9305fb 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3466,7 +3466,7 @@ build_vex_prefix (const insn_template *t)
static INLINE bfd_boolean
is_evex_encoding (const insn_template *t)
{
- return t->opcode_modifier.evex
+ return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
|| t->opcode_modifier.broadcast || t->opcode_modifier.masking
|| t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
}
@@ -3889,6 +3889,8 @@ optimize_encoding (void)
&& is_evex_encoding (&i.tm)
&& (i.vec_encoding != vex_encoding_evex
|| i.tm.cpu_flags.bitfield.cpuavx512vl
+ || (i.tm.operand_types[2].bitfield.zmmword
+ && i.types[2].bitfield.ymmword)
|| cpu_arch_isa_flags.bitfield.cpuavx512vl)))
&& ((i.tm.base_opcode == 0x55
|| i.tm.base_opcode == 0x6655
@@ -5210,8 +5212,47 @@ check_VecOperands (const insn_template *t)
{
if (i.broadcast)
i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
- else
+ else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
i.memshift = t->opcode_modifier.disp8memshift;
+ else
+ {
+ const i386_operand_type *type = NULL;
+
+ i.memshift = 0;
+ for (op = 0; op < i.operands; op++)
+ if (operand_type_check (i.types[op], anymem))
+ {
+ if (t->operand_types[op].bitfield.xmmword
+ + t->operand_types[op].bitfield.ymmword
+ + t->operand_types[op].bitfield.zmmword <= 1)
+ type = &t->operand_types[op];
+ else if (!i.types[op].bitfield.unspecified)
+ type = &i.types[op];
+ }
+ else if (i.types[op].bitfield.regsimd)
+ {
+ if (i.types[op].bitfield.zmmword)
+ i.memshift = 6;
+ else if (i.types[op].bitfield.ymmword && i.memshift < 5)
+ i.memshift = 5;
+ else if (i.types[op].bitfield.xmmword && i.memshift < 4)
+ i.memshift = 4;
+ }
+
+ if (type)
+ {
+ if (type->bitfield.zmmword)
+ i.memshift = 6;
+ else if (type->bitfield.ymmword)
+ i.memshift = 5;
+ else if (type->bitfield.xmmword)
+ i.memshift = 4;
+ }
+
+ /* For the check in fits_in_disp8(). */
+ if (i.memshift == 0)
+ i.memshift = -1;
+ }
for (op = 0; op < i.operands; op++)
if (operand_type_check (i.types[op], disp)
diff --git a/gas/testsuite/gas/i386/noavx512-2.l b/gas/testsuite/gas/i386/noavx512-2.l
index 08febef..c846251 100644
--- a/gas/testsuite/gas/i386/noavx512-2.l
+++ b/gas/testsuite/gas/i386/noavx512-2.l
@@ -5,8 +5,8 @@
.*:30: Error: .*unsupported instruction.*
.*:32: Error: .*unsupported instruction.*
.*:33: Error: .*unsupported instruction.*
-.*:36: Error: .*unsupported masking.*
-.*:37: Error: .*unsupported masking.*
+.*:36: Error: .*unsupported instruction.*
+.*:37: Error: .*unsupported instruction.*
.*:39: Error: .*unsupported instruction.*
.*:40: Error: .*unsupported instruction.*
.*:43: Error: .*unsupported instruction.*