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2021-04-01Remove strneq macro and use startswith.Martin Liska4-17/+23
bfd/ChangeLog: * ecoff.c (strneq): Remove strneq and use startswith. (_bfd_ecoff_slurp_armap): Likewise. binutils/ChangeLog: * elfcomm.h (strneq): Remove strneq and use startswith. * readelf.c (ia64_process_unwind): Likewise. (process_note): Likewise. gas/ChangeLog: * config/obj-coff.c (strneq): Remove strneq and use startswith. (weak_is_altname): Likewise. (obj_coff_section): Likewise. * config/tc-cr16.c (process_label_constant): Likewise. * config/tc-crx.c (strneq): Likewise. include/ChangeLog: * opcode/cr16.h (strneq): Remove strneq and use startswith. ld/ChangeLog: * ldbuildid.c (strneq): Remove strneq and use startswith. (validate_build_id_style): Likewise. (compute_build_id_size): Likewise. opcodes/ChangeLog: * arm-dis.c (strneq): Remove strneq and use startswith. * cr16-dis.c (print_insn_cr16): Likewise. * score-dis.c (streq): Likewise. (strneq): Likewise. * score7-dis.c (strneq): Likewise.
2021-04-01Use startswith in gas subfolder.Martin Liska58-417/+540
gas/ChangeLog: * as.c (select_emulation_mode): Use startswith. * config/m68k-parse.y: Likewise. * config/obj-aout.c (obj_aout_type): Likewise. * config/obj-elf.c (elf_common_parse): Likewise. (obj_elf_section_type): Likewise. (obj_elf_section_word): Likewise. (obj_elf_section): Likewise. (obj_elf_symver): Likewise. (adjust_stab_sections): Likewise. * config/obj-evax.c (evax_shorten_name): Likewise. * config/obj-macho.c (obj_mach_o_is_frame_section): Likewise. * config/tc-aarch64.c (parse_aarch64_imm_float): Likewise. (aarch64_parse_features): Likewise. (create_register_alias): Likewise. (aarch64_data_in_code): Likewise. (md_parse_option): Likewise. * config/tc-alpha.c (s_alpha_section_word): Likewise. (s_alpha_pdesc): Likewise. * config/tc-arc.c (tokenize_extregister): Likewise. * config/tc-arm.c (create_register_alias): Likewise. (create_neon_reg_alias): Likewise. (parse_ifimm_zero): Likewise. (parse_qfloat_immediate): Likewise. (arm_elf_section_type): Likewise. (arm_parse_extension): Likewise. (aeabi_set_public_attributes): Likewise. (s_arm_arch_extension): Likewise. (arm_data_in_code): Likewise. (start_unwind_section): Likewise. * config/tc-avr.c (avr_ldi_expression): Likewise. * config/tc-csky.c (is_freglist_legal): Likewise. (csky_s_section): Likewise. * config/tc-d30v.c (do_assemble): Likewise. * config/tc-dlx.c (parse_operand): Likewise. * config/tc-epiphany.c (md_assemble): Likewise. * config/tc-h8300.c (h8300_elf_section): Likewise. (get_operand): Likewise. * config/tc-hppa.c (pa_ip): Likewise. (pa_level): Likewise. (pa_space): Likewise. * config/tc-i386.c (i386_mach): Likewise. (md_assemble): Likewise. (check_VecOperations): Likewise. (i386_target_format): Likewise. (i386_elf_section_type): Likewise. * config/tc-ia64.c (start_unwind_section): Likewise. (md_parse_option): Likewise. (is_taken_branch): Likewise. (idesc->name,): Likewise. (note_register_values): Likewise. (do_alias): Likewise. * config/tc-m32c.c (insn_to_subtype): Likewise. * config/tc-m68hc11.c (get_operand): Likewise. (md_assemble): Likewise. * config/tc-m68k.c (m68k_ip): Likewise. (m68k_elf_suffix): Likewise. * config/tc-mcore.c (mcore_s_section): Likewise. * config/tc-metag.c (parse_get_set): Likewise. (md_parse_option): Likewise. * config/tc-microblaze.c (parse_imm): Likewise. (check_got): Likewise. (md_apply_fix): Likewise. * config/tc-mips.c (CPU_HAS_MIPS16): Likewise. (md_begin): Likewise. (s_is_linkonce): Likewise. (check_regno): Likewise. (match_float_constant): Likewise. (classify_vr4120_insn): Likewise. (match_insn): Likewise. (mips_after_parse_args): Likewise. (s_change_sec): Likewise. (s_option): Likewise. (parse_code_option): Likewise. (md_section_align): Likewise. (nopic_need_relax): Likewise. * config/tc-mmix.c (mmix_handle_mmixal): Likewise. * config/tc-mn10300.c (mn10300_fix_adjustable): Likewise. (mn10300_end_of_match): Likewise. * config/tc-msp430.c (msp430_make_init_symbols): Likewise. * config/tc-nds32.c (nds32_parse_option): Likewise. * config/tc-nds32.h (md_do_align): Likewise. * config/tc-nios2.c (strprefix): Likewise. (nios2_special_relocation_p): Likewise. (nios2_parse_base_register): Likewise. (nios2_cons): Likewise. * config/tc-ns32k.c (addr_mode): Likewise. * config/tc-pdp11.c (set_option): Likewise. (parse_reg): Likewise. (parse_ac5): Likewise. (parse_op_no_deferred): Likewise. (set_cpu_model): Likewise. (set_machine_model): Likewise. * config/tc-pj.c (md_operand): Likewise. * config/tc-ppc.c (ppc_set_cpu): Likewise. (ppc_arch): Likewise. (ppc_section_type): Likewise. * config/tc-s12z.c (tb_reg_rel): Likewise. (tb_opr_rel): Likewise. * config/tc-s390.c (s390_parse_cpu): Likewise. (md_parse_option): Likewise. * config/tc-score.c (s3_nopic_need_relax): Likewise. (s3_pic_need_relax): Likewise. * config/tc-score7.c (s7_nopic_need_relax): Likewise. (s7_pic_need_relax): Likewise. * config/tc-sh.h (SUB_SEGMENT_ALIGN): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. (sparc_ip): Likewise. (s_reserve): Likewise. (s_common): Likewise. (s_seg): Likewise. (sparc_cons): Likewise. * config/tc-tic54x.c (stag_add_field): Likewise. (tic54x_endstruct): Likewise. * config/tc-tic6x.c (tic6x_start_unwind_section): Likewise. * config/tc-v850.c (v850_comm): Likewise. (md_begin): Likewise. (md_assemble): Likewise. * config/tc-vax.c (vax_cons): Likewise. * config/tc-wasm32.c (wasm32_leb128): Likewise. * config/tc-xstormy16.c (md_operand): Likewise. * config/tc-xtensa.c (get_directive): Likewise. (xg_instruction_matches_option_term): Likewise. (is_unaligned_label): Likewise. (cache_literal_section): Likewise. * config/xtensa-relax.c (parse_precond): Likewise. (parse_option_cond): Likewise. (transition_applies): Likewise. (wide_branch_opcode): Likewise. * dw2gencfi.c: Likewise. * dwarf2dbg.c (dwarf2_directive_filename): Likewise. * ehopt.c (get_cie_info): Likewise. * input-file.c (input_file_open): Likewise. * listing.c (listing_newline): Likewise. (debugging_pseudo): Likewise. * read.c (read_a_source_file): Likewise. * write.c (adjust_reloc_syms): Likewise. (compress_debug): Likewise. (maybe_generate_build_notes): Likewise.
2021-03-31Don't include bfd/sysdep.h for gas filesAlan Modra5-7/+11
* itbl-lex-wrapper.c: Include as.h not sysdep.h. * config/bfin-lex-wrapper.c: Likewise. * itbl-lex.l: Don't include as.h. * config/bfin-lex.l: Likewise.
2021-03-31Use bool in gasAlan Modra133-4237/+4275
* as.h (POISON_BFD_BOOLEAN): Define. * as.c, * as.h, * atof-generic.c, * config/atof-ieee.c, * config/bfin-aux.h, * config/obj-coff.c, * config/obj-ecoff.c, * config/obj-elf.c, * config/obj-elf.h, * config/obj-som.c, * config/tc-aarch64.c, * config/tc-alpha.c, * config/tc-arc.c, * config/tc-arc.h, * config/tc-arm.c, * config/tc-arm.h, * config/tc-avr.c, * config/tc-avr.h, * config/tc-bfin.c, * config/tc-bfin.h, * config/tc-bpf.c, * config/tc-cris.c, * config/tc-csky.c, * config/tc-csky.h, * config/tc-d10v.c, * config/tc-d10v.h, * config/tc-d30v.c, * config/tc-d30v.h, * config/tc-dlx.c, * config/tc-dlx.h, * config/tc-epiphany.c, * config/tc-epiphany.h, * config/tc-fr30.c, * config/tc-fr30.h, * config/tc-frv.c, * config/tc-frv.h, * config/tc-ft32.c, * config/tc-ft32.h, * config/tc-h8300.c, * config/tc-hppa.c, * config/tc-i386-intel.c, * config/tc-i386.c, * config/tc-ia64.c, * config/tc-ip2k.c, * config/tc-iq2000.c, * config/tc-iq2000.h, * config/tc-lm32.c, * config/tc-lm32.h, * config/tc-m32c.c, * config/tc-m32c.h, * config/tc-m32r.c, * config/tc-m32r.h, * config/tc-m68hc11.c, * config/tc-m68k.c, * config/tc-mcore.c, * config/tc-mcore.h, * config/tc-mep.c, * config/tc-mep.h, * config/tc-metag.c, * config/tc-metag.h, * config/tc-microblaze.c, * config/tc-mips.c, * config/tc-mips.h, * config/tc-mmix.c, * config/tc-mn10200.c, * config/tc-mn10300.c, * config/tc-mn10300.h, * config/tc-moxie.c, * config/tc-msp430.c, * config/tc-msp430.h, * config/tc-mt.c, * config/tc-mt.h, * config/tc-nds32.c, * config/tc-nds32.h, * config/tc-nios2.c, * config/tc-ns32k.c, * config/tc-or1k.c, * config/tc-or1k.h, * config/tc-pdp11.c, * config/tc-ppc.c, * config/tc-pru.c, * config/tc-pru.h, * config/tc-riscv.c, * config/tc-riscv.h, * config/tc-rx.c, * config/tc-rx.h, * config/tc-s12z.c, * config/tc-s12z.h, * config/tc-s390.c, * config/tc-score.c, * config/tc-score.h, * config/tc-score7.c, * config/tc-sh.c, * config/tc-sh.h, * config/tc-spu.c, * config/tc-tic54x.c, * config/tc-tic6x.c, * config/tc-tic6x.h, * config/tc-tilegx.c, * config/tc-tilepro.c, * config/tc-v850.c, * config/tc-v850.h, * config/tc-visium.c, * config/tc-visium.h, * config/tc-wasm32.c, * config/tc-wasm32.h, * config/tc-xc16x.c, * config/tc-xgate.c, * config/tc-xstormy16.c, * config/tc-xstormy16.h, * config/tc-xtensa.c, * config/tc-xtensa.h, * config/tc-z80.c, * config/tc-z8k.c, * config/xtensa-istack.h, * config/xtensa-relax.c, * config/xtensa-relax.h, * dw2gencfi.c, * dwarf2dbg.c, * dwarf2dbg.h, * expr.c, * expr.h, * frags.c, * frags.h, * listing.c, * macro.c, * output-file.c, * read.c, * read.h, * stabs.c, * symbols.c, * write.c: Replace bfd_boolean with bool, FALSE with false, and TRUE with true.
2021-03-31Remove bfd_stdint.hAlan Modra5-4/+10
If we require C99 for binutils then stdint.h is available. bfd/ * .gitignore: Delete bfd_stdint.h entry. * Makefile.am (bfdinclude_HEADERS): Delete bfd_stdint.h. (BUILD_HFILES, LOCAL_H_DEPS): Likewise. * bfd-in.h: Include stdint.h in place of bfd_stdint.h. * configure.ac: Don't invoke GCC_HEADER_STDINT. * configure.com: Don't create bfd_stdint.h. * Makefile.in: Regenerate. * aclocal.m4: Regenerate. * bfd-in2.h: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. binutils/ * coffdump.c: Include stdint.h in place of bfd_stdint.h. * dwarf.c: Likewise. gas/ * config/tc-aarch64.c: Include stdint.h in place of bfd_stdint.h. * config/tc-crx.c: Likewise. * config/tc-nds32.h: Likewise. include/ * cgen/basic-modes.h: Include stdint.h in place of bfd_stdint.h. * elf/nfp.h: Likewise. * opcode/aarch64.h: Likewise. * opcode/cgen.h: Likewise. * opcode/nfp.h: Likewise. * opcode/ppc.h: Likewise. ld/ * elf-hints-local.h: Include stdint.h in place of bfd_stdint.h. * emultempl/nds32elf.em: Likewise. * testsuite/ld-elf/mbind2b.c: Likewise. * testsuite/ld-elf/pr18718.c: Likewise. * testsuite/ld-elf/pr18720a.c: Likewise. * testsuite/ld-elf/pr25749-1.c: Likewise. * testsuite/ld-elf/pr25749-1a.c: Likewise. * testsuite/ld-elf/pr25749-1b.c: Likewise. * testsuite/ld-elf/pr25749-1c.c: Likewise. * testsuite/ld-elf/pr25749-1d.c: Likewise. * testsuite/ld-elf/pr25749-2.c: Likewise. * testsuite/ld-elf/pr25754-1a.c: Likewise. * testsuite/ld-elf/pr25754-2a.c: Likewise. * testsuite/ld-elf/pr25754-3a.c: Likewise. * testsuite/ld-elf/pr25754-4a.c: Likewise. * testsuite/ld-elf/pr25754-5a.c: Likewise. * testsuite/ld-elf/pr25754-6a.c: Likewise. opcodes/ * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. * aarch64-dis.h: Likewise. * aarch64-opc.c: Likewise. * avr-dis.c: Likewise. * csky-dis.c: Likewise. * nds32-asm.c: Likewise. * nds32-dis.c: Likewise. * nfp-dis.c: Likewise. * riscv-dis.c: Likewise. * s12z-dis.c: Likewise. * wasm32-dis.c: Likewise.
2021-03-30x86: drop seg_entryJan Beulich3-45/+46
Use struct reg_entry instead for most purposes, with a separate array holding just the respective opcode prefix bytes.
2021-03-30x86: drop REGNAM_{AL,AX,EAX}Jan Beulich3-3/+17
The former two are unused anyway. And having such constants isn't very helpful either, when they live in a place where updating the register table wouldn't even allow noticing the need to adjust these constants.
2021-03-30x86: adjust st(<N>) parsingJan Beulich2-6/+29
st(1) ... st(7) will never be looked up in the hash table, so there's no point inserting the entries. It's also not really necessary to do a 2nd hash lookup after parsing the register number, nor is there a real reason for having both st and st(0) entries. Plus we can easily do away with the need for st to be first in the table.
2021-03-30x86: integrate rc_op into struct _i386_insnJan Beulich2-43/+50
There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of rounding being in effect off of the type field of the structure instead.
2021-03-30x86: integrate broadcast_op into struct _i386_insnJan Beulich2-43/+52
There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of broadcast being in effect off of the type field of the structure instead.
2021-03-30x86: integrate mask_op into struct _i386_insnJan Beulich2-55/+69
There's no need for the extra level of indirection and the extra storage needed for the pointer, pointing from one piece of static data to another. Key checking of masking being in effect off of the register field of the structure instead.
2021-03-30x86: make swap_2_operands() have unsigned parametersJan Beulich2-12/+25
All callers pass unsigned values (in some cases by virtue of passing non-negative literal numbers). This in turn requires struct {Mask,RC,Broadcast}_Operation's "operand" fields to become unsigned, in turn allowing to reduce the amount of casting needed (the two new casts that are necessary cast _to_ "unsigned" instead of _from_, as that's the form that'll never case undefined behavior).
2021-03-29x86: VPSADBW's source operands are also commutativeJan Beulich4-2/+10
In commit 79dec6b7baa2 ("x86-64: optimize certain commutative VEX-encoded insns") I missed the fact that there being subtraction involved here doesn't matter, as absolute differences get summed up.
2021-03-29x86: derive opcode encoding space attribute from base opcodeJan Beulich3-120/+173
Just like is already done for VEX/XOP/EVEX encoded insns, record the encoding space information in the respective opcode modifier field. Do this again without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-29TRUE/FALSE simplificationAlan Modra17-82/+59
There is really no need to write code like "foo != 0 ? TRUE : FALSE" unless we had stupidly defined FALSE as something other than 0 or TRUE as something other than 1. The simpler "foo != 0" does just as well. Similarly "(condition == TRUE)" or "(condition == FALSE) can be simplified to "(condition)" and "(!condition)" respectively. I'll note that there is reason to use "integer_expression != 0" when assigning a bfd_boolean rather than the simpler "integer_expression", if you expect the variable to have 0 or 1 value. It's probably even a good idea to not rely on implicit conversion if bfd_boolean were _Bool. bfd/ * aoutx.h (aout_link_write_symbols): Don't cast boolean expression to bfd_boolean. * elf32-or1k.c (or1k_set_got_and_rela_sizes): Dont compare booleans against FALSE. * elf32-arc.c (name_for_global_symbol): Don't compare boolean to TRUE. (is_reloc_PC_relative): Don't use "boolean_condition ? TRUE : FALSE". (is_reloc_SDA_relative, is_reloc_for_GOT): Likewise. (is_reloc_for_PLT, is_reloc_for_TLS): Likewise. * elf32-arm.c (stm32l4xx_need_create_replacing_stub): Likewise. * elf32-nds32.c (insert_nds32_elf_blank): Likewise. * elf32-rx.c (rx_set_section_contents): Likewise. * elfnn-aarch64.c (elfNN_aarch64_final_link_relocate): Likewise. * elfxx-mips.c (_bfd_mips_elf_ignore_undef_symbol): Likewise. * mach-o.c (bfd_mach_o_read_command): Likewise. * targets.c (bfd_get_target_info): Likewise. binutils/ * dlltool.c (main): Don't use "boolean_condition ? TRUE : FALSE". * dwarf.c (read_and_display_attr_value): Likewise. (display_debug_str_offsets): Likewise. * objdump.c (dump_bfd): Likewise. * readelf.c (dump_section_as_strings): Likewise. (dump_section_as_bytes): Likewise. gas/ * atof-generic.c (FALSE, TRUE): Don't define. * config/obj-elf.h (FALSE, TRUE): Don't define. * config/obj-som.h (FALSE, TRUE): Don't define. * config/tc-hppa.h (FALSE, TRUE): Don't define. * config/tc-pdp11.c (FALSE, TRUE): Don't define. * config/tc-iq2000.h (obj_fix_adjustable): Delete. * config/tc-m32r.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-mt.h (obj_fix_adjustable): Delete. * config/tc-nds32.h (TC_FIX_ADJUSTABLE): Delete. * config/tc-arc.c (parse_opcode_flags): Simplify boolean expression. (relaxable_flag, relaxable_operand, assemble_insn): Likewise. (tokenize_extregister): Likewise. * config/tc-csky.c (parse_opcode, get_operand_value): Likewise. (parse_operands_op, parse_operands, md_assemble): Likewise. * config/tc-d10v.c (build_insn): Likewise. * config/tc-score.c (s3_gen_insn_frag): Likewise. * config/tc-score7.c (s7_gen_insn_frag, s7_relax_frag): Likewise. * config/tc-tic6x.c (tic6x_update_features, md_assemble): Likewise. * config/tc-z80.c (emit_byte): Likewise. include/ * opcode/aarch64.h (alias_opcode_p): Simplify boolean expression. (opcode_has_alias, pseudo_opcode_p, optional_operand_p): Likewise. (opcode_has_special_coder): Likewise. ld/ * emultempl/aix.em (gld${EMULATION_NAME}_before_allocation): Simplify boolean expression. * lexsup.c (parse_args): Likewise. * pe-dll.c (pe_dll_id_target): Likewise. opcodes/ * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. (fp_qualifier_p, get_data_pattern): Likewise. (aarch64_get_operand_modifier_from_value): Likewise. (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. (operand_variant_qualifier_p): Likewise. (qualifier_value_in_range_constraint_p): Likewise. (aarch64_get_qualifier_esize): Likewise. (aarch64_get_qualifier_nelem): Likewise. (aarch64_get_qualifier_standard_value): Likewise. (get_lower_bound, get_upper_bound): Likewise. (aarch64_find_best_match, match_operands_qualifier): Likewise. (aarch64_print_operand): Likewise. * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. (operand_need_sign_extension, operand_need_shift_by_two): Likewise. (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. (print_insn_tic6x): Likewise.
2021-03-29gas int vs bfd_boolean fixesAlan Modra7-65/+83
* config/tc-arm.c (struct arm_long_option_table <func>): Return bfd_boolean. * config/tc-arm.h (arm_optimize_expr, arm_data_in_code): Likewise. * config/tc-metag.c (parse_mov_port): Replace unsigned int variable with bfd_boolean. (parse_mmov, parse_mov_ct, parse_alu, parse_shift, parse_bitop), (parse_cmp, parse_fmmov, parse_fmov_data, parse_fearith), (parse_dget_set, parse_dalu): Likewise, ensuring assignment from logical expressions. (struct metag_long_option <func>): Return bfd_boolean. (metag_parse_cpu, metag_parse_fpu, metag_parse_dsp): Likewise. * config/tc-msp430.c (msp430_dstoperand): Correct dummy type. * config/tc-s12z.c (parse_operand_func): Return bfd_boolean. (no_operands, lex_force_match, lex_reg_list): Likewise. (size_from_suffix): Return int. (s12z_relax_frag, md_estimate_size_before_relax): Return 0. * config/tc-s12z.h (tc_s12z_fix_adjustable): Likewise.
2021-03-26x86-64: don't accept supposedly disabled MOVQ formsJan Beulich4-0/+31
While all of MMX, SSE, and SSE2 are included in "generic64", they can be individually disabled. There are two MOVQ forms lacking respective attributes. While the MMX one would get refused anyway (due to MMX registers not recognized with .nommx), the assembler did happily accept the SSE2 form. Add respective CPU settings to both, paralleling what the MOVD counterparts have.
2021-03-25[NIOS2] Fix disassembly of br.n instruction.Hafiz Abid Qadeer3-0/+19
The code was checking wrong bit for sign extension. It caused it to zero-extend instead of sign-extend the immediate value. 2021-03-25 Abid Qadeer <abidh@codesourcery.com> opcodes/ * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of immediate in br.n instruction. gas/ * testsuite/gas/nios2/brn.s: New. * testsuite/gas/nios2/brn.d: New.
2021-03-25x86: fix CMPXCHG8B special case when disallowing q suffix outside of 64-bit modeJan Beulich2-1/+5
In match_template() i.tm hasn't been filled yet, so it is necessarily t which needs checking. This is only a latent issue as no other templates with the same base_opcode have an extension_opcode of 1.
2021-03-25x86: flag bad S/G insn operand combinationsJan Beulich12-176/+90
For VEX-encoded ones, all three involved vector registers have to be distinct. For EVEX-encoded ones an actual mask register has to be in use and zeroing-masking cannot be used (violation of either will #UD). Additionally both involved vector registers have to be distinct for EVEX-encoded gathers.
2021-03-25x86: flag as bad AVX512 insns with EVEX.z set but EVEX.aaa clearJan Beulich3-1/+11
This combination makes no sense and is documented to cause #UD.
2021-03-25x86: fix AMD Zen3 insnsJan Beulich8-28/+97
For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
2021-03-25x86-64: limit breakage from gcc movdir64b et al workaroundJan Beulich16-35/+178
This is only a partial fix for PR/gas 27419, in that it limits the bad behavior of accepting mismatched operands to just x32 mode. The full fix would be to revert commits 27f134698ac5 and b3a3496f83a1, and to address the issue in gcc instead.
2021-03-25PR27647 PowerPC extended conditional branch mnemonicsAlan Modra3-8/+14
opcodes/ PR 27647 * ppc-opc.c (XLOCB_MASK): Delete. (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using XLBH_MASK. (powerpc_opcodes): Accept a BH field on all extended forms of bclr, bclrl, bcctr, bcctrl, bctar, bctarl. gas/ PR 27647 * testsuite/gas/ppc/a2.d: Update expected output. * testsuite/gas/ppc/power8.d: Likewise.
2021-03-24x86: derive opcode length from opcode valueJan Beulich2-16/+46
In the majority of cases we can easily determine the length from the encoding, irrespective of whether a prefix is specified there as well. We further don't even need to record the value in the table entries, as it's easy enough to determine it (without any guesswork, unless an insn with major opcode 00 appeared that requires a 2nd opcode byte to be specified explicitly) when installing the chosen template for further processing. Should an encoding appear which - has a major opcode byte of 66, F3, or F2, - requires a 2nd opcode byte to be specified explicitly, - doesn't have a mandatory prefix we'd need to convert all templates presently encoding a mandatory prefix this way to the Prefix_0X<nn> model to eliminate the respective guessing i386-gen does.
2021-03-24x86: derive mandatory prefix attribute from base opcodeJan Beulich3-73/+63
Just like is already done for legacy encoded insns, record the mandatory prefix information in the respective opcode modifier field. Do this without changing the source table, but rather by deriving the values from their existing source representation.
2021-03-24x86: don't use opcode_length to identify pseudo prefixesJan Beulich2-2/+8
This is in preparation of opcode_length going away as a field in the templates. Identify pseudo prefixes by a base opcode of zero instead: No real prefix has an opcode of zero. This at the same time allows dropping a curious special case from i386-gen. Since most attributes are identical for all pseudo prefixes, take the opportunity and also template them.
2021-03-23x86: re-number PREFIX_0X<nn>Jan Beulich2-1/+5
In preparation to use PREFIX_0X<nn> attributes also in VEX/XOP/EVEX encoding templates, renumber the pseudo-enumerators such that their values can then also be used directly in the respective prefix bit fields.
2021-03-23x86: re-order two fields of struct insn_templateJan Beulich1-0/+6
To facilitate a subsequent table parser change, re-order CPU flags and opcode modifier fields. No functional change intended.
2021-03-23x86: split opcode prefix and opcode space representationJan Beulich2-48/+33
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") used the opcodeprefix field for two distinct purposes. In preparation of having VEX/XOP/EVEX and non-VEX templates become similar in the representatioon of both encoding space and opcode prefixes, split the field to have a separate one holding an insn's opcode space.
2021-03-23x86: don't open-code PREFIX_NONEJan Beulich2-11/+12
Use the constant rather than literal zero. While at it fold two conditionals (using the same base opcode and prefix) in load_insn_p().
2021-03-23x86: unbreak certain MPX insn operand formsJan Beulich5-27/+55
Commit 8b65b8953af2 ("x86: Remove the prefix byte from non-VEX/EVEX base_opcode") dropped the mandatory prefix bytes from legacy encoded insn templates, but failed to also adjust affected MPX-specific checks in two places. For the expressions to remain halfway readable, introduce local variables to hold current_templates->start.
2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska3-5/+11
bfd/ChangeLog: * bfd-in.h (startswith): Add startswith function. (CONST_STRNEQ): Remove. * bfd-in2.h (startswith): Regenerate with make headers. * archive.c (bfd_slurp_armap): Replace usage of CONST_STRNEQ with startswith. (_bfd_slurp_extended_name_table): Likewise. * archive64.c (_bfd_archive_64_bit_slurp_armap): Likewise. * bfd.c (bfd_get_sign_extend_vma): Likewise. (bfd_convert_section_size): Likewise. (bfd_convert_section_contents): Likewise. * coff-stgo32.c (go32exe_create_stub): Likewise. (go32exe_check_format): Likewise. * coffcode.h (styp_to_sec_flags): Likewise. (GNU_DEBUGALTLINK): Likewise. * coffgen.c (_bfd_coff_section_already_linked): Likewise. (coff_gc_sweep): Likewise. (bfd_coff_gc_sections): Likewise. * cofflink.c (coff_link_add_symbols): Likewise. (process_embedded_commands): Likewise. * compress.c (bfd_is_section_compressed_with_header): Likewise. (bfd_init_section_decompress_status): Likewise. * dwarf2.c (find_debug_info): Likewise. (place_sections): Likewise. * ecoff.c (_bfd_ecoff_slurp_armap): Likewise. * elf-m10300.c (_bfd_mn10300_elf_size_dynamic_sections): Likewise. * elf.c (_bfd_elf_make_section_from_shdr): Likewise. (assign_section_numbers): Likewise. (elfcore_grok_win32pstatus): Likewise. * elf32-arm.c (cmse_scan): Likewise. (elf32_arm_gc_mark_extra_sections): Likewise. (elf32_arm_size_dynamic_sections): Likewise. (is_arm_elf_unwind_section_name): Likewise. * elf32-bfin.c (bfin_size_dynamic_sections): Likewise. * elf32-cr16.c (_bfd_cr16_elf_size_dynamic_sections): Likewise. * elf32-cris.c (elf_cris_size_dynamic_sections): Likewise. * elf32-csky.c (csky_elf_size_dynamic_sections): Likewise. * elf32-hppa.c (elf32_hppa_size_dynamic_sections): Likewise. * elf32-iq2000.c (iq2000_elf_check_relocs): Likewise. * elf32-lm32.c (lm32_elf_size_dynamic_sections): Likewise. * elf32-m32r.c (m32r_elf_size_dynamic_sections): Likewise. * elf32-m68k.c (elf_m68k_size_dynamic_sections): Likewise. * elf32-metag.c (elf_metag_size_dynamic_sections): Likewise. * elf32-msp430.c (msp430_elf_relax_delete_bytes): Likewise. * elf32-nios2.c (nios2_elf32_size_dynamic_sections): Likewise. * elf32-or1k.c (or1k_elf_size_dynamic_sections): Likewise. * elf32-ppc.c (ppc_elf_size_dynamic_sections): Likewise. * elf32-s390.c (elf_s390_size_dynamic_sections): Likewise. * elf32-score.c (s3_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-score7.c (s7_bfd_score_elf_size_dynamic_sections): Likewise. * elf32-sh.c (sh_elf_size_dynamic_sections): Likewise. * elf32-tic6x.c (is_tic6x_elf_unwind_section_name): Likewise. (elf32_tic6x_size_dynamic_sections): Likewise. * elf32-vax.c (elf_vax_size_dynamic_sections): Likewise. * elf32-xtensa.c (elf_xtensa_size_dynamic_sections): Likewise. (xtensa_is_insntable_section): Likewise. (xtensa_is_littable_section): Likewise. (xtensa_is_proptable_section): Likewise. (xtensa_property_section_name): Likewise. (xtensa_callback_required_dependence): Likewise. * elf64-alpha.c (elf64_alpha_size_dynamic_sections): Likewise. * elf64-hppa.c (elf64_hppa_size_dynamic_sections): Likewise. * elf64-ia64-vms.c (is_unwind_section_name): Likewise. (get_reloc_section): Likewise. (elf64_ia64_size_dynamic_sections): Likewise. (elf64_ia64_object_p): Likewise. * elf64-mmix.c (mmix_elf_add_symbol_hook): Likewise. * elf64-ppc.c (ppc64_elf_size_dynamic_sections): Likewise. * elf64-s390.c (elf_s390_size_dynamic_sections): Likewise. * elflink.c (elf_link_add_object_symbols): Likewise. (_bfd_elf_gc_mark_extra_sections): Likewise. (bfd_elf_parse_eh_frame_entries): Likewise. (_bfd_elf_section_already_linked): Likewise. * elfnn-aarch64.c (elfNN_aarch64_size_dynamic_sections): Likewise. * elfnn-ia64.c (is_unwind_section_name): Likewise. (elfNN_ia64_size_dynamic_sections): Likewise. (elfNN_ia64_object_p): Likewise. * elfxx-mips.c (FN_STUB_P): Likewise. (CALL_STUB_P): Likewise. (CALL_FP_STUB_P): Likewise. (_bfd_mips_elf_section_from_shdr): Likewise. (_bfd_mips_elf_fake_sections): Likewise. (_bfd_mips_elf_size_dynamic_sections): Likewise. (_bfd_mips_final_write_processing): Likewise. (_bfd_mips_elf_final_link): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elfxx-x86.c (elf_i386_is_reloc_section): Likewise. (elf_x86_64_is_reloc_section): Likewise. * hpux-core.c (thread_section_p): Likewise. * libcoff.h (bfd_pei_p): Likewise. * linker.c (REAL): Likewise. (unwrap_hash_lookup): Likewise. (_bfd_generic_link_add_one_symbol): Likewise. * mmo.c (mmo_internal_write_section): Likewise. * osf-core.c (osf_core_core_file_p): Likewise. * pef.c (bfd_pef_print_symbol): Likewise. * pei-x86_64.c (pex64_print_all_pdata_sections): Likewise. * som.c (som_slurp_symbol_table): Likewise. (som_slurp_armap): Likewise. * wasm-module.c (wasm_compute_custom_section_file_position): Likewise. binutils/ChangeLog: * dlltool.c (scan_drectve_symbols): Replace usage of CONST_STRNEQ with startswith. * emul_aix.c (ar_emul_aix_parse_arg): Likewise. * objcopy.c (is_mergeable_note_section): Likewise. * objdump.c (dump_dwarf_section): Likewise. * prdbg.c (pr_method_type): Likewise. (pr_class_baseclass): Likewise. (tg_class_baseclass): Likewise. * readelf.c (process_lto_symbol_tables): Likewise. * stabs.c (ULLHIGH): Likewise. (parse_stab_argtypes): Likewise. (stab_demangle_function_name): Likewise. gas/ChangeLog: * config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith. (x86_64_section_word): Likewise. * config/tc-sparc.c (md_parse_option): Likewise. gdb/ChangeLog: * arm-tdep.c (show_disassembly_style_sfunc): Replace usage of CONST_STRNEQ with startswith. (_initialize_arm_tdep): Likewise. ld/ChangeLog: * emultempl/aix.em: Replace usage of CONST_STRNEQ with startswith. * emultempl/beos.em: Likewise. * emultempl/elf.em: Likewise. * emultempl/pe.em: Likewise. * emultempl/pep.em: Likewise. * emultempl/xtensaelf.em: Likewise. * ldctor.c (ctor_prio): Likewise. * ldelf.c (ldelf_try_needed): Likewise. (ldelf_parse_ld_so_conf): Likewise. (ldelf_after_open): Likewise. (output_rel_find): Likewise. (ldelf_place_orphan): Likewise. * ldfile.c (ldfile_add_library_path): Likewise. * ldlang.c (lang_add_input_file): Likewise. * ldmain.c (get_sysroot): Likewise. (get_emulation): Likewise. (add_archive_element): Likewise. * ldwrite.c (unsplittable_name): Likewise. (clone_section): Likewise. * lexsup.c (parse_args): Likewise. * pe-dll.c (is_import): Likewise. (pe_implied_import_dll): Likewise. opcodes/ChangeLog: * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. * arc-dis.c (parse_option): Likewise. * arm-dis.c (parse_arm_disassembler_options): Likewise. * cris-dis.c (print_with_operands): Likewise. * h8300-dis.c (bfd_h8_disassemble): Likewise. * i386-dis.c (print_insn): Likewise. * ia64-gen.c (fetch_insn_class): Likewise. (parse_resource_users): Likewise. (in_iclass): Likewise. (lookup_specifier): Likewise. (insert_opcode_dependencies): Likewise. * mips-dis.c (parse_mips_ase_option): Likewise. (parse_mips_dis_option): Likewise. * s390-dis.c (disassemble_init_s390): Likewise. * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
2021-03-19gas/app.c don't throw away spaces before slashAlan Modra2-1/+4
I don't know really why we should lose a space before a '/'. Possibly it would make sense if '/' started a comment, but otherwise no. * app.c (do_scrub_chars): Don't lose spaces before a slash.
2021-03-182021-03-18 Christian Groessler <chris@groessler.org>Christian Groessler2-16/+31
* config/tc-z8k.c (apply_fix): Handle 7-bit relocations correctly. Problem found by Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>.
2021-03-16RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructionsKuan-Lin Chen6-0/+170
bfd/ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc. gas/ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc. (riscv_multi_subset_supports): Add INSN_CLASS_ZB*. * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case. * testsuite/gas/riscv/b-ext-64.d: Likewise. * testsuite/gas/riscv/b-ext.s: Likewise. * testsuite/gas/riscv/b-ext.d: Likewise. include/ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions. * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*. opcodes/ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
2021-03-12aarch64: Add few missing system registersPrzemyslaw Wirkus6-0/+59
This patch adds few missing system registers to GAS: LORC_EL1, LOREA_EL1, LORN_EL1, LORSA_EL1, ICC_CTLR_EL3, ICC_SRE_ELX, ICH_VTR_EL2. gas/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * testsuite/gas/aarch64/illegal-sysreg-7.d: New test. * testsuite/gas/aarch64/illegal-sysreg-7.l: New test. * testsuite/gas/aarch64/illegal-sysreg-7.s: New test. * testsuite/gas/aarch64/sysreg-7.d: New test. * testsuite/gas/aarch64/sysreg-7.s: New test. opcodes/ChangeLog: 2021-03-02 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
2021-03-12aix: implement TLS relocation for gas and ldClément Chigot3-45/+226
Add support for TLS in XCOFF. Amongst the things done by this commit: - Update XCOFF auxialiary header to match new version and allow TLS sections. - Add TLS sections (.tdata and .tbss) support in gas and ld. - Add support for the TLS relocations in gas and ld. Two different types BFD_RELOC are created for PPC and PPC64 as the size is a pointer, thus distinct in 32 or 64bit. The addresses given by ld to .tdata and .tbss is a bit special. In XCOFF, these addresses are actually offsets from the TLS pointer computed at runtime. AIX assembly and linker does the same. In top of that, the .tdata must be before .data (this is mandatory for AIX loader). Thus, the aix ld script is recomputing "." before .data to restore its original value. There might be a simpler way, but this one is working. Optimisation linked to TLS relocations aren't yet implemented. bfd/ * reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE, BFD_RELOC_PPC_TLS_M, BFD_RELOC_PPC_TLS_ML, BFD_RELOC_PPC64_TLS_GD, BFD_RELOC_PPC64_TLS_LD, BFD_RELOC_PPC64_TLS_LE, BFD_RELOC_PPC64_TLS_IE, BFD_RELOC_PPC64_TLS_M, BFD_RELOC_PPC64_TLS_ML): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_tls for TLS relocations. (xcoff_howto_table): Implement TLS relocations. (_bfd_xcoff_reloc_type_lookup): Add cases TLS relocations. (xcoff_reloc_type_tls): New function. * coff64-rs6000.c (xcoff_calculate_relocation): Likewise. (xcoff_howto_table): Likewise. (_bfd_xcoff_reloc_type_lookup): Likewise. * coffcode.h (sec_to_styp_flags): Handle TLS sections. (styp_to_sec_flags): Likewise. (coff_compute_section_file_positions): Avoid file offset optimisation for .data when the previous section is .tdata. (coff_write_object_contents): Handle TLS sections. * coffswap.h (coff_swap_aouthdr_out): Add support for new fields in aouthdr. * libxcoff.h (xcoff_reloc_type_tls): Add prototype. * xcofflink.c (xcoff_link_add_symbols): Handle XMC_UL. (xcoff_need_ldrel_p): Add cases for TLS relocations. (xcoff_create_ldrel): Add l_symndx for TLS sections. gas/ * config/tc-ppc.c (ppc_xcoff_text_section, ppc_xcoff_data_section, (ppc_xcoff_bss_section, ppc_xcoff_tdata_section, (ppc_xcoff_tbss_section): New variables. (ppc_text_subsegment, ppc_text_csects, ppc_data_subgments, (ppc_data_csects): Removed. (ppc_xcoff_section_is_initialized, ppc_init_xcoff_section, ppc_xcoff_parse_cons): New functions. (md_being): Initialize XCOFF sections. (ppc_xcoff_suffix): Add support for TLS relocations (fixup_size, md_apply_fix): Add support for new BFD_RELOC. (ppc_change_csect): Handle XMC_TL, XMC_UL. Correctly, add XMC_BS to .bss section. Handle new XCOFF section variables. (ppc_comm): Likewise. (ppc_toc): Likewise. (ppc_symbol_new_hook): Likewise. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Add tbss support. * config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): New define. (ppc_xcoff_parse_cons): Add prototype. (struct ppc_xcoff_section): New structure. ld/ * emultempl/aix.em: Ensure .tdata section is removed if empty, even with -r flag. * scripttempl/aix.sc: Handle TLS sections. * testsuite/ld-powerpc/aix52.exp: Add new tests. * testsuite/ld-powerpc/aix-tls-reloc-32.d: New test. * testsuite/ld-powerpc/aix-tls-reloc-64.d: New test. * testsuite/ld-powerpc/aix-tls-reloc.ex: New test. * testsuite/ld-powerpc/aix-tls-reloc.s: New test. * testsuite/ld-powerpc/aix-tls-section-32.d: New test. * testsuite/ld-powerpc/aix-tls-section-64.d: New test. * testsuite/ld-powerpc/aix-tls-section.ex: New test. * testsuite/ld-powerpc/aix-tls-section.s: New test. include/ * coff/internal.h (struct internal_aouthdr): Add new fields. * coff/rs6000.h (AOUTHDRÃ): Add new fields. * coff/rs6k64.h (struct external_filehdr): Likewise. * coff/xcoff.h (_TDATA), _TBSS): New defines (RS6K_AOUTHDR_TLS_LE, RS6K_AOUTHDR_RAS, RS6K_AOUTHDR_ALGNTDATA, RS6K_AOUTHDR_SHR_SYMTAB, RS6K_AOUTHDR_FORK_POLICY, RS6K_AOUTHDR_FORK_COR): New defines. (XMC_TU): Removed. (XMC_UL): New define.
2021-03-12aix: implement R_TOCU and R_TOCL relocationsClément Chigot2-8/+163
Implement support for largetoc on XCOFF. R_TOCU and R_TOCL are referenced by the new BFD defines: BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. A new toc storage class is added XMC_TE. In order to correctly handle R_TOCU, the logic behind xcoff_reloc_type_toc is changed to compute the whole TOC offset instead of just the difference between the "link" offset and the "assembly" offset. In gas, add a function to transform addis format used by AIX "addis RT, D(RA)" into the ELF format "addis RT, RA, SI". bfd/ * reloc.c (BFD_RELOC_PPC_TOC16_HI, BFD_RELOC_PPC_TOC16_LO): New relocations. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * coff-rs6000.c (xcoff_calculate_relocation): Call xcoff_reloc_type_toc for R_TOCU and R_TOCL. (xcoff_howto_table): Remove src_mask for TOC relocations. Add R_TOCU and R_TOCL howtos. (_bfd_xcoff_reloc_type_lookup): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (xcoff_reloc_type_toc): Compute the whole offset. Implement R_TOCU and R_TOCL. * coff64-rs6000.c (xcoff64_calculate_relocation): Likewise. (xcoff64_howto_table): Likewise. (xcoff64_reloc_type_lookup): Likewise. gas/ * config/tc-ppc.c (ppc_xcoff_suffix): New function. (MAP, MAP32, MAP64): New macros for XCOFF. (ppc_xcoff_fixup_addis): New function. (ppc_is_toc_sym): Handle XMC_TE. (fixup_size): Add cases for BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. (md_assemble): Call ppc_xcoff_fixup_addis for XCOFF. (ppc_change_csect): Handle XMC_TE. (ppc_tc): Enable .tc symbols to have only a XMC_TC or XMC_TE storage class. (ppc_symbol_new_hook): Handle XMC_TE. (ppc_frob_symbol): Likewise. (ppc_fix_adjustable): Likewise. (md_apply_fix): Handle BFD_RELOC_PPC_TOC16_HI and BFD_RELOC_PPC_TOC16_LO. ld/ * scripttempl/aix.sc: Add .te to .data section. * testsuite/ld-powerpc/aix52.exp: Add test structure for AIX7+. Add aix-largetoc-1 test. * testsuite/ld-powerpc/aix-largetoc-1-32.d: New test. * testsuite/ld-powerpc/aix-largetoc-1-64.d: New test. * testsuite/ld-powerpc/aix-largetoc-1.ex: New test. * testsuite/ld-powerpc/aix-largetoc-1.s: New test.
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich7-930/+939
Commit 6ff00b5e12e7 ("x86/Intel: correct permitted operand sizes for AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn handling in line with AVX2's, but the disassembler side was forgotten. This has the benefit of - allowing to fold a number of table entries, - rendering a few #define-s and enumerators unused.
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich8-16/+2372
All encodings not used in this range are (reserved) NOPs. Hence their decoding should be fully consistent. For this to work the PREFIX_IGNORED logic needs slightly extending, such that the attribute will also - have an effect when used inside prefix_table[], yet without always falling back to using slot 0, - cause prefixes marked as ignored while decoding through prefix_table[] to no longer be considered decoded, when encountered in a subsequent decoding step. In adjacent code also drop meaningless PREFIX_OPCODE.
2021-03-09x86: fold some prefix related attributes into a single oneJan Beulich2-9/+19
RepPrefixOk, HLEPrefixOk, and NoTrackPrefixOk can't be specified together, so can share an enum-like field. IsLockable can be inferred from HLE setting and hence only needs specifying when neither of them is present.
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich12-7/+36
Despite SYSEXIT being an Intel-only insn in long mode, its behavior there is similar to SYSRET's: Depending on REX.W execution continues in either 64-bit or compatibility mode. Hence distinguishing by suffix is as necessary here as it is there.
2021-02-26Correct an error message in the ARM assembler.Nick Clifton5-1/+31
PR 27411 * config/tc-arm.c (do_t_add_sub): Correct error message. * testsuite/gas/arm/pr27411.s: New test. * testsuite/gas/arm/pr27411.d: New test driver. * testsuite/gas/arm/pr27411.l: Expected error output for new test.
2021-02-24PR23691, gas .y files vs. automatic make dependenciesAlan Modra8-216/+125
A number of targets, bfin, rl78, rx, can show odd failures when bfd/reloc.c changes BFD_RELOC_* enum values, if recompiling over a build dir with existing objects. The problem is caused by bfin-parse.o and similar not being recompiled and so using stale BFD_RELOC_* values. This isn't fixed by making bfin-parse.c depend on bfd/reloc.c, which isn't necessary anyway. bfin-parse.o should have been recompiled due to bfd/bfd.h changing when extracted bfd/reloc.c BFD_RELOC_* values change, but that wasn't happening. The problem is that automake generates a makefile that loads gas/config/.deps/ dependency file for objects with corresponding sources mentioned in EXTRA_as_new_SOURCES. Unless we want to mess around generating explicit dependencies, I think that mean moving some object files to the build gas/config/. This patch does that, removing some hacks for m68k-parse.c that should no longer be necessary, and removes some rules that catered to old bison producing code that triggers compiler warnings. PR 23691 * Makefile.am (TARGET_CPU_CFILES): Split off config/xtensa-relax.c.. (TARGET_CPU_HFILES): ..and config/xtensa-relax.h.. (TARGET_EXTRA_FILES): ..to here. Add config/bfin-lex-wrapper.c, and use alongside TARGET_CPU_CFILES. (EXTRA_DIST): Update location of generated .c files. (config/m68k-parse.c): New rule replacing m68k-parse.c rule. (config/bfin-parse.c, config/rl78-parse.cm config/rx-parse.c), (config/bfin-lex.c, config/bfin-lex-wrapper.@OBJEXT@): Similarly. (itbl-lex-wrapper.@OBJEXT@): Simplify to just the needed dependencies. (itbl-parse.@OBJEXT@): Delete rule using NO_WERROR. (itbl-parse.c, itbl-parse.h): Tidy. * config/bfin-lex-wrapper.c: Include config/bfin-lex.c. * config/bfin-lex.l: Include config/bfin-parse.h. * configure.ac (extra_objects): Move object files corresponding to .y and .l files now in config/ to config/. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2021-02-19Fix compile time warnings when building riscv assembler.Nick Clifton2-3/+8
* config/tc-riscv.c (riscv_ip): Fix compile time warnings about misleading indentation.
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu5-175/+228
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types, [VALID/EXTRACT/ENCODE macros] BTYPE_IMM: Renamed from SBTYPE_IMM. JTYPE_IMM: Renamed from UJTYPE_IMM. CITYPE_IMM: Renamed from RVC_IMM. CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM. CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM. CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM. CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM. CIWTYPE_IMM: Renamed from RVC_UIMM8. CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM. CSSTYPE_IMM: Added for .insn without special encoding. CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM. CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM. CLTYPE_IMM: Added for .insn without special encoding. CLTYPE_LW_IMM: Renamed from RVC_LW_IMM. CLTYPE_LD_IMM: Renamed from RVC_LD_IMM. RVC_SIMM3: Unused and removed. CBTYPE_IMM: Renamed from RVC_B_IMM. CJTYPE_IMM: Renamed from RVC_J_IMM. * Added new operands and removed the unused ones, C5: Unsigned CL(CS) immediate, added for .insn directive. C6: Unsigned CSS immediate, added for .insn directive. Ci: Unused and removed. C<: Unused and removed. bfd/ PR 27158 * elfnn-riscv.c (perform_relocation): Updated encoding macros. (_bfd_riscv_relax_call): Likewise. (_bfd_riscv_relax_lui): Likewise. * elfxx-riscv.c (howto_table): Likewise. gas/ PR 27158 * config/tc-riscv.c (riscv_ip): Updated encoding macros. (md_apply_fix): Likewise. (md_convert_frag_branch): Likewise. (validate_riscv_insn): Likewise. Also arranged operands, including added C5 and C6 operands, and removed unused Ci and C< operands. * doc/c-riscv.texi: Updated and added CSS/CL/CS types. * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions. * testsuite/gas/riscv/insn.s: Likewise. gdb/ PR 27158 * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros. (decode_j_type_insn): Likewise. (decode_cj_type_insn): Likewise. (decode_b_type_insn): Likewise. (decode): Likewise. include/ PR 27158 * opcode/riscv.h: Updated encoding macros. opcodes/ PR 27158 * riscv-dis.c (print_insn_args): Updated encoding macros. * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. (match_c_addi16sp): Updated encoding macros. (match_c_lui): Likewise. (match_c_lui_with_hint): Likewise. (match_c_addi4spn): Likewise. (match_c_slli): Likewise. (match_slli_as_c_slli): Likewise. (match_c_slli64): Likewise. (match_srxi_as_c_srxi): Likewise. (riscv_insn_types): Added .insn css/cl/cs. sim/ PR 27158 * riscv/sim-main.c (execute_i): Updated encoding macros.
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu2-24/+126
Make the opcode/riscv-opc.c and include/opcode/riscv.h tidy, move the spec versions stuff to bfd/cpu-riscv.h. Also move the csr stuff and ext_version_table to gas/config/tc-riscv.c for internal use. To avoid too many repeated code, define general RISCV_GET_SPEC_NAME/SPEC_CLASS macros. Therefore, assembler/dis-assembler/linker/gdb can get all spec versions related stuff from cpu-riscv.h and cpu-riscv.c, since the stuff are defined there uniformly. bfd/ * Makefile.am: Added cpu-riscv.h. * Makefile.in: Regenerated. * po/SRC-POTFILES.in: Regenerated. * cpu-riscv.h: Added to support spec versions controlling. Also added extern arrays and functions for cpu-riscv.c. (enum riscv_spec_class): Define all spec classes here uniformly. (struct riscv_spec): Added for all specs. (RISCV_GET_SPEC_CLASS): Added to reduce repeated code. (RISCV_GET_SPEC_NAME): Likewise. (RISCV_GET_ISA_SPEC_CLASS): Added to get ISA spec class. (RISCV_GET_PRIV_SPEC_CLASS): Added to get privileged spec class. (RISCV_GET_PRIV_SPEC_NAME): Added to get privileged spec name. * cpu-riscv.c (struct priv_spec_t): Replaced with struct riscv_spec. (riscv_get_priv_spec_class): Replaced with RISCV_GET_PRIV_SPEC_CLASS. (riscv_get_priv_spec_name): Replaced with RISCV_GET_PRIV_SPEC_NAME. (riscv_priv_specs): Moved below. (riscv_get_priv_spec_class_from_numbers): Likewise, updated. (riscv_isa_specs): Moved from include/opcode/riscv.h. * elfnn-riscv.c: Included cpu-riscv.h. (riscv_merge_attributes): Initialize in_priv_spec and out_priv_spec. * elfxx-riscv.c: Included cpu-riscv.h and opcode/riscv.h. (RISCV_UNKNOWN_VERSION): Moved from include/opcode/riscv.h. * elfxx-riscv.h: Removed extern functions to cpu-riscv.h. gas/ * config/tc-riscv.c: Included cpu-riscv.h. (enum riscv_csr_clas): Moved from include/opcode/riscv.h. (struct riscv_csr_extra): Likewise. (struct riscv_ext_version): Likewise. (ext_version_table): Moved from opcodes/riscv-opc.c. (default_isa_spec): Updated type to riscv_spec_class. (default_priv_spec): Likewise. (riscv_set_default_isa_spec): Updated. (init_ext_version_hash): Likewise. (riscv_init_csr_hash): Likewise, also fixed indent. include/ * opcode/riscv.h: Moved stuff and make the file tidy. opcodes/ * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. (default_priv_spec): Updated type to riscv_spec_class. (parse_riscv_dis_option): Updated. * riscv-opc.c: Moved stuff and make the file tidy.
2021-02-17h8300 complains about new section defined without attributesAlan Modra2-0/+5
* testsuite/gas/elf/section28.d: xfail h8300.
2021-02-16gas: Allow SHF_GNU_RETAIN on all sectionsH.J. Lu7-6/+66
Since SHF_GNU_RETAIN is allowed on all sections, strip SHF_GNU_RETAIN when checking incorrect section attributes. PR gas/27412 * config/obj-elf.c (obj_elf_change_section): Strip SHF_GNU_RETAIN when checking incorrect section attributes. * testsuite/gas/elf/elf.exp: Run section28 and section29. * testsuite/gas/elf/section28.d: New file. * testsuite/gas/elf/section28.s: Likewise. * testsuite/gas/elf/section29.d: Likewise. * testsuite/gas/elf/section29.s: Likewise.
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