RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.

* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,

[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM:            Renamed from SBTYPE_IMM.
JTYPE_IMM:            Renamed from UJTYPE_IMM.
CITYPE_IMM:           Renamed from RVC_IMM.
CITYPE_LUI_IMM:       Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM:  Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM:      Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM:      Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM:          Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM:          Added for .insn without special encoding.
CSSTYPE_SWSP_IMM:     Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM:     Renamed from RVC_SDSP_IMM.
CLTYPE_IMM:           Added for .insn without special encoding.
CLTYPE_LW_IMM:        Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM:        Renamed from RVC_LD_IMM.
RVC_SIMM3:            Unused and removed.
CBTYPE_IMM:           Renamed from RVC_B_IMM.
CJTYPE_IMM:           Renamed from RVC_J_IMM.

* Added new operands and removed the unused ones,

C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.

bfd/
    PR 27158
    * elfnn-riscv.c (perform_relocation): Updated encoding macros.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    * elfxx-riscv.c (howto_table): Likewise.
gas/
    PR 27158
    * config/tc-riscv.c (riscv_ip): Updated encoding macros.
    (md_apply_fix): Likewise.
    (md_convert_frag_branch): Likewise.
    (validate_riscv_insn): Likewise.  Also arranged operands, including
    added C5 and C6 operands, and removed unused Ci and C< operands.
    * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
    * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
    * testsuite/gas/riscv/insn.s: Likewise.
gdb/
    PR 27158
    * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
    (decode_j_type_insn): Likewise.
    (decode_cj_type_insn): Likewise.
    (decode_b_type_insn): Likewise.
    (decode): Likewise.
include/
    PR 27158
    * opcode/riscv.h: Updated encoding macros.
opcodes/
    PR 27158
    * riscv-dis.c (print_insn_args): Updated encoding macros.
    * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
    (match_c_addi16sp): Updated encoding macros.
    (match_c_lui): Likewise.
    (match_c_lui_with_hint): Likewise.
    (match_c_addi4spn): Likewise.
    (match_c_slli): Likewise.
    (match_slli_as_c_slli): Likewise.
    (match_c_slli64): Likewise.
    (match_srxi_as_c_srxi): Likewise.
    (riscv_insn_types): Added .insn css/cl/cs.
sim/
    PR 27158
    * riscv/sim-main.c (execute_i): Updated encoding macros.

5 files changed, 228 insertions, 175 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index a90ab78..ae1bd92 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2021-02-19  Nelson Chu  <nelson.chu@sifive.com>
+
+	PR 27158
+	* config/tc-riscv.c (riscv_ip): Updated encoding macros.
+	(md_apply_fix): Likewise.
+	(md_convert_frag_branch): Likewise.
+	(validate_riscv_insn): Likewise.  Also arranged operands, including
+	added C5 and C6 operands, and removed unused Ci and C< operands.
+	* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
+	* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
+	* testsuite/gas/riscv/insn.s: Likewise.
+
 2021-02-18  Nelson Chu  <nelson.chu@sifive.com>
 
 	* config/tc-riscv.c: Included cpu-riscv.h.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 44450d7..5f4f3ec 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -996,36 +996,37 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
       case 'C': /* RVC */
 	switch (c = *p++)
 	  {
-	  case 'a': used_bits |= ENCODE_RVC_J_IMM (-1U); break;
-	  case 'c': break; /* RS1, constrained to equal sp.  */
-	  case 'i': used_bits |= ENCODE_RVC_SIMM3(-1U); break;
-	  case 'j': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case 'o': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case 'k': used_bits |= ENCODE_RVC_LW_IMM (-1U); break;
-	  case 'l': used_bits |= ENCODE_RVC_LD_IMM (-1U); break;
-	  case 'm': used_bits |= ENCODE_RVC_LWSP_IMM (-1U); break;
-	  case 'n': used_bits |= ENCODE_RVC_LDSP_IMM (-1U); break;
-	  case 'p': used_bits |= ENCODE_RVC_B_IMM (-1U); break;
+	  case 'U': break; /* CRS1, constrained to equal RD.  */
+	  case 'c': break; /* CRS1, constrained to equal sp.  */
+	  case 'T': /* CRS2, floating point.  */
+	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
+	  case 'S': /* CRS1S, floating point.  */
 	  case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
+	  case 'w': break; /* CRS1S, constrained to equal RD.  */
+	  case 'D': /* CRS2S, floating point.  */
 	  case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
-	  case 'u': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case 'v': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case 'w': break; /* RS1S, constrained to equal RD.  */
-	  case 'x': break; /* RS2S, constrained to equal RD.  */
-	  case 'z': break; /* RS2S, constrained to be x0.  */
-	  case 'K': used_bits |= ENCODE_RVC_ADDI4SPN_IMM (-1U); break;
-	  case 'L': used_bits |= ENCODE_RVC_ADDI16SP_IMM (-1U); break;
-	  case 'M': used_bits |= ENCODE_RVC_SWSP_IMM (-1U); break;
-	  case 'N': used_bits |= ENCODE_RVC_SDSP_IMM (-1U); break;
-	  case 'U': break; /* RS1, constrained to equal RD.  */
-	  case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
-	  case '<': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case '>': used_bits |= ENCODE_RVC_IMM (-1U); break;
-	  case '8': used_bits |= ENCODE_RVC_UIMM8 (-1U); break;
-	  case 'S': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break;
-	  case 'T': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break;
-	  case 'D': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break;
-	  case 'F': /* RVC funct for .insn directive.  */
+	  case 'x': break; /* CRS2S, constrained to equal RD.  */
+	  case 'z': break; /* CRS2S, constrained to be x0.  */
+	  case '>': /* CITYPE immediate, compressed shift.  */
+	  case 'u': /* CITYPE immediate, compressed lui.  */
+	  case 'v': /* CITYPE immediate, li to compressed lui.  */
+	  case 'o': /* CITYPE immediate, allow zero.  */
+	  case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break;
+	  case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break;
+	  case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break;
+	  case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break;
+	  case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break;
+	  case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break;
+	  case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break;
+	  case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break;
+	  case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break;
+	  /* CLTYPE and CSTYPE have the same immediate encoding.  */
+	  case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break;
+	  case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break;
+	  case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break;
+	  case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break;
+	  case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break;
+	  case 'F': /* Compressed funct for .insn directive.  */
 	    switch (c = *p++)
 	      {
 		case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break;
@@ -1051,34 +1052,36 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
       case ')': break;
       case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break;
       case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
-      case 'A': break;
-      case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
-      case 'Z': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
-      case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
-      case 'I': break;
-      case 'R': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
-      case 'S': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
-      case 'U': USE_BITS (OP_MASK_RS1, OP_SH_RS1);
-	/* Fall through.  */
-      case 'T': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
+      case 'A': break; /* Macro operand, must be symbol.  */
+      case 'B': break; /* Macro operand, must be symbol or constant.  */
+      case 'I': break; /* Macro operand, must be constant.  */
+      case 'D': /* RD, floating point.  */
       case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
-      case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
+      case 'Z': /* RS1, CSR number.  */
+      case 'S': /* RS1, floating point.  */
       case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break;
+      case 'U': /* RS1 and RS2 are the same, floating point.  */
+	USE_BITS (OP_MASK_RS1, OP_SH_RS1);
+	/* Fall through.  */
+      case 'T': /* RS2, floating point.  */
       case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
-      case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3);     break;
+      case 'R': /* RS3, floating point.  */
+      case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
+      case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
+      case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
       case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
       case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break;
-      case 'o':
+      case 'o': /* ITYPE immediate, load displacement.  */
       case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break;
-      case 'a': used_bits |= ENCODE_UJTYPE_IMM (-1U); break;
-      case 'p': used_bits |= ENCODE_SBTYPE_IMM (-1U); break;
+      case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break;
+      case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break;
       case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break;
       case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break;
-      case 'z': break;
-      case '[': break;
-      case ']': break;
-      case '0': break;
-      case '1': break;
+      case 'z': break; /* Zero immediate.  */
+      case '[': break; /* Unused operand.  */
+      case ']': break; /* Unused operand.  */
+      case '0': break; /* AMO displacement, must to zero.  */
+      case '1': break; /* Relaxation operand.  */
       case 'F': /* Funct for .insn directive.  */
 	switch (c = *p++)
 	  {
@@ -2078,82 +2081,83 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      || imm_expr->X_add_number <= 0
 		      || imm_expr->X_add_number >= 64)
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
 		rvc_imm_done:
 		  s = expr_end;
 		  imm_expr->X_op = O_absent;
 		  continue;
-		case '<':
+		case '5':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || imm_expr->X_add_number <= 0
+		      || imm_expr->X_add_number < 0
 		      || imm_expr->X_add_number >= 32
-		      || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+		    ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
-		case '8':
+		case '6':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
 		      || imm_expr->X_add_number < 0
-		      || imm_expr->X_add_number >= 256
-		      || !VALID_RVC_UIMM8 ((valueT) imm_expr->X_add_number))
+		      || imm_expr->X_add_number >= 64
+		      || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_UIMM8 (imm_expr->X_add_number);
+		    ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
-		case 'i':
+		case '8':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || imm_expr->X_add_number == 0
-		      || !VALID_RVC_SIMM3 ((valueT) imm_expr->X_add_number))
+		      || imm_expr->X_add_number < 0
+		      || imm_expr->X_add_number >= 256
+		      || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_SIMM3 (imm_expr->X_add_number);
+		    ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'j':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
 		      || imm_expr->X_add_number == 0
-		      || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'k':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_LW_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_LW_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'l':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_LD_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_LD_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'm':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_LWSP_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_LWSP_IMM (imm_expr->X_add_number);
+		    ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'n':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_LDSP_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_LDSP_IMM (imm_expr->X_add_number);
+		    ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'o':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
@@ -2161,47 +2165,46 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      /* C.addiw, c.li, and c.andi allow zero immediate.
 			 C.addi allows zero immediate as hint.  Otherwise this
 			 is same as 'j'.  */
-		      || !VALID_RVC_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'K':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
 		      || imm_expr->X_add_number == 0
-		      || !VALID_RVC_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_ADDI4SPN_IMM (imm_expr->X_add_number);
+		    ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'L':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || imm_expr->X_add_number == 0
-		      || !VALID_RVC_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_ADDI16SP_IMM (imm_expr->X_add_number);
+		    ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'M':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_SWSP_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_SWSP_IMM (imm_expr->X_add_number);
+		    ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'N':
 		  if (riscv_handle_implicit_zero_offset (imm_expr, s))
 		    continue;
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
 		      || imm_expr->X_op != O_constant
-		      || !VALID_RVC_SDSP_IMM ((valueT) imm_expr->X_add_number))
+		      || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number))
 		    break;
 		  ip->insn_opcode |=
-		    ENCODE_RVC_SDSP_IMM (imm_expr->X_add_number);
+		    ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'u':
 		  p = percent_op_utype;
@@ -2215,7 +2218,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 			  && (imm_expr->X_add_number <
 			      RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2)))
 		    break;
-		  ip->insn_opcode |= ENCODE_RVC_IMM (imm_expr->X_add_number);
+		  ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number);
 		  goto rvc_imm_done;
 		case 'v':
 		  if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
@@ -3114,7 +3117,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  /* Fill in a tentative value to improve objdump readability.  */
 	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
 	  bfd_vma delta = target - md_pcrel_from (fixP);
-	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_UJTYPE_IMM (delta), buf);
+	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf);
 	}
       break;
 
@@ -3124,7 +3127,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  /* Fill in a tentative value to improve objdump readability.  */
 	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
 	  bfd_vma delta = target - md_pcrel_from (fixP);
-	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_SBTYPE_IMM (delta), buf);
+	  bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf);
 	}
       break;
 
@@ -3134,7 +3137,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  /* Fill in a tentative value to improve objdump readability.  */
 	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
 	  bfd_vma delta = target - md_pcrel_from (fixP);
-	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_B_IMM (delta), buf);
+	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf);
 	}
       break;
 
@@ -3144,7 +3147,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	  /* Fill in a tentative value to improve objdump readability.  */
 	  bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP;
 	  bfd_vma delta = target - md_pcrel_from (fixP);
-	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_RVC_J_IMM (delta), buf);
+	  bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf);
 	}
       break;
 
@@ -3530,7 +3533,7 @@ md_convert_frag_branch (fragS *fragp)
 	    /* Invert the branch condition.  Branch over the jump.  */
 	    insn = bfd_getl16 (buf);
 	    insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ;
-	    insn |= ENCODE_RVC_B_IMM (6);
+	    insn |= ENCODE_CBTYPE_IMM (6);
 	    bfd_putl16 (insn, buf);
 	    buf += 2;
 	    goto jump;
@@ -3557,7 +3560,7 @@ md_convert_frag_branch (fragS *fragp)
       /* Invert the branch condition.  Branch over the jump.  */
       insn = bfd_getl32 (buf);
       insn ^= MATCH_BEQ ^ MATCH_BNE;
-      insn |= ENCODE_SBTYPE_IMM (8);
+      insn |= ENCODE_BTYPE_IMM (8);
       bfd_putl32 (insn, buf);
       buf += 4;
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index e945482..c15297e 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -363,7 +363,7 @@ The pseudo la.tls.gd instruction can be expended to
 @cindex instruction formats, risc-v
 @cindex RISC-V instruction formats
 
-The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 12
+The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15
 instruction formats where some of the formats have multiple variants.
 For the @samp{.insn} pseudo directive the assembler recognizes some
 of the formats.
@@ -394,6 +394,8 @@ only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
 @item simm12 @tab Sign-extended 12-bit immediate for operand x.
 @item simm20 @tab Sign-extended 20-bit immediate for operand x.
 @item simm6 @tab Sign-extended 6-bit immediate for operand x.
+@item uimm5 @tab Unsigned 5-bit immediate for operand x.
+@item uimm6 @tab Unsigned 6-bit immediate for operand x.
 @item uimm8 @tab Unsigned 8-bit immediate for operand x.
 @item symbol @tab Symbol or lable reference for operand x.
 @end multitable
@@ -487,112 +489,136 @@ The following table lists the RISC-V instruction formats that are available
 with the @samp{.insn} pseudo directive:
 
 @table @code
-@item R type: .insn r opcode, func3, func7, rd, rs1, rs2
+@item R type: .insn r opcode6, func3, func7, rd, rs1, rs2
 @verbatim
-+-------+-----+-----+-------+----+-------------+
-| func7 | rs2 | rs1 | func3 | rd |      opcode |
-+-------+-----+-----+-------+----+-------------+
-31      25    20    15      12   7             0
++-------+-----+-----+-------+----+---------+
+| func7 | rs2 | rs1 | func3 | rd | opcode6 |
++-------+-----+-----+-------+----+---------+
+31      25    20    15      12   7        0
 @end verbatim
 
-@item R type with 4 register operands: .insn r opcode, func3, func2, rd, rs1, rs2, rs3
-@itemx R4 type: .insn r4 opcode, func3, func2, rd, rs1, rs2, rs3
+@item R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
+@itemx R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
 @verbatim
-+-----+-------+-----+-----+-------+----+-------------+
-| rs3 | func2 | rs2 | rs1 | func3 | rd |      opcode |
-+-----+-------+-----+-----+-------+----+-------------+
-31    27      25    20    15      12   7             0
++-----+-------+-----+-----+-------+----+---------+
+| rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
++-----+-------+-----+-----+-------+----+---------+
+31    27      25    20    15      12   7         0
 @end verbatim
 
-@item I type: .insn i opcode, func3, rd, rs1, simm12
-@itemx I type: .insn i opcode, func3, rd, simm12(rs1)
+@item I type: .insn i opcode6, func3, rd, rs1, simm12
+@itemx I type: .insn i opcode6, func3, rd, simm12(rs1)
 @verbatim
-+-------------+-----+-------+----+-------------+
-|      simm12 | rs1 | func3 | rd |      opcode |
-+-------------+-----+-------+----+-------------+
-31            20    15      12   7             0
++--------------+-----+-------+----+---------+
+| simm12[11:0] | rs1 | func3 | rd | opcode6 |
++--------------+-----+-------+----+---------+
+31             20    15      12   7         0
 @end verbatim
 
-@item S type: .insn s opcode, func3, rs2, simm12(rs1)
+@item S type: .insn s opcode6, func3, rs2, simm12(rs1)
 @verbatim
-+--------------+-----+-----+-------+-------------+-------------+
-| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] |      opcode |
-+--------------+-----+-----+-------+-------------+-------------+
-31             25    20    15      12            7             0
++--------------+-----+-----+-------+-------------+---------+
+| simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
++--------------+-----+-----+-------+-------------+---------+
+31             25    20    15      12            7         0
 @end verbatim
 
-@item B type: .insn s opcode, func3, rs1, rs2, symbol
-@itemx SB type: .insn sb opcode, func3, rs1, rs2, symbol
+@item B type: .insn s opcode6, func3, rs1, rs2, symbol
+@itemx SB type: .insn sb opcode6, func3, rs1, rs2, symbol
 @verbatim
-+------------+--------------+-----+-----+-------+-------------+-------------+--------+
-| simm12[12] | simm12[10:5] | rs2 | rs1 | func3 | simm12[4:1] | simm12[11]] | opcode |
-+------------+--------------+-----+-----+-------+-------------+-------------+--------+
-31          30            25    20    15      12           7            0
++-----------------+-----+-----+-------+----------------+---------+
+| simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
++-----------------+-----+-----+-------+----------------+---------+
+31                25    20    15      12               7         0
 @end verbatim
 
-@item U type: .insn u opcode, rd, simm20
+@item U type: .insn u opcode6, rd, simm20
 @verbatim
-+---------------------------+----+-------------+
-|                    simm20 | rd |      opcode |
-+---------------------------+----+-------------+
-31                          12   7             0
++--------------------------+----+---------+
+| simm20[20|10:1|11|19:12] | rd | opcode6 |
++--------------------------+----+---------+
+31                         12   7         0
 @end verbatim
 
-@item J type: .insn j opcode, rd, symbol
-@itemx UJ type: .insn uj opcode, rd, symbol
+@item J type: .insn j opcode6, rd, symbol
+@itemx UJ type: .insn uj opcode6, rd, symbol
 @verbatim
-+------------+--------------+------------+---------------+----+-------------+
-| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd |      opcode |
-+------------+--------------+------------+---------------+----+-------------+
-31           30             21           20              12   7             0
++------------+--------------+------------+---------------+----+---------+
+| simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
++------------+--------------+------------+---------------+----+---------+
+31           30             21           20              12   7         0
 @end verbatim
 
 @item CR type: .insn cr opcode2, func4, rd, rs2
 @verbatim
-+---------+--------+-----+---------+
-|   func4 | rd/rs1 | rs2 | opcode2 |
-+---------+--------+-----+---------+
-15        12       7     2        0
++-------+--------+-----+---------+
+| func4 | rd/rs1 | rs2 | opcode2 |
++-------+--------+-----+---------+
+15      12       7     2        0
 @end verbatim
 
 @item CI type: .insn ci opcode2, func3, rd, simm6
 @verbatim
-+---------+-----+--------+-----+---------+
-|   func3 | imm | rd/rs1 | imm | opcode2 |
-+---------+-----+--------+-----+---------+
-15        13    12       7     2         0
++-------+----------+--------+------------+---------+
+| func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
++-------+----------+--------+------------+---------+
+15      13         12       7            2         0
 @end verbatim
 
-@item CIW type: .insn ciw opcode2, func3, rd, uimm8
+@item CIW type: .insn ciw opcode2, func3, rd', uimm8
 @verbatim
-+---------+--------------+-----+---------+
-|   func3 |          imm | rd' | opcode2 |
-+---------+--------------+-----+---------+
-15        13             7     2         0
++-------+------------+-----+---------+
+| func3 | uimm8[7:0] | rd' | opcode2 |
++-------+-------- ---+-----+---------+
+15      13           5     2         0
 @end verbatim
 
-@item CA type: .insn ca opcode2, func6, func2, rd, rs2
+@item CSS type: .insn css opcode2, func3, rd, uimm6
 @verbatim
-+---------+----------+-------+------+--------+
-|   func6 | rd'/rs1' | func2 | rs2' | opcode |
-+---------+----------+-------+------+--------+
-15        10         7       5      2        0
++-------+------------+----+---------+
+| func3 | uimm6[5:0] | rd | opcode2 |
++-------+------------+----+---------+
+15      13           7    2         0
 @end verbatim
 
-@item CB type: .insn cb opcode2, func3, rs1, symbol
+@item CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
 @verbatim
-+---------+--------+------+--------+---------+
-|   func3 | offset | rs1' | offset | opcode2 |
-+---------+--------+------+--------+---------+
-15        13       10     7        2         0
++-------+------------+------+------------+------+---------+
+| func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
++-------+------------+------+------------+------+---------+
+15      13           10     7            5      2         0
+@end verbatim
+
+@item CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
+@verbatim
++-------+------------+------+------------+------+---------+
+| func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
++-------+------------+------+------------+------+---------+
+15      13           10     7            5      2         0
+@end verbatim
+
+@item CA type: .insn ca opcode2, func6, func2, rd', rs2'
+@verbatim
++-- ----+----------+-------+------+---------+
+| func6 | rd'/rs1' | func2 | rs2' | opcode2 |
++-------+----------+-------+------+---------+
+15      10         7       5      2         0
+@end verbatim
+
+@item CB type: .insn cb opcode2, func3, rs1', symbol
+@verbatim
++-------+--------------+------+------------------+---------+
+| func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
++-------+--------------+------+------------------+---------+
+15      13             10     7                  2         0
 @end verbatim
 
 @item CJ type: .insn cj opcode2, symbol
 @verbatim
-+---------+--------------------+---------+
-|   func3 |        jump target | opcode2 |
-+---------+--------------------+---------+
-15        13             7     2         0
++-------+-------------------------------+---------+
+| func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
++-------+-------------------------------+---------+
+15      13                              2         0
 @end verbatim
 
 
diff --git a/gas/testsuite/gas/riscv/insn.d b/gas/testsuite/gas/riscv/insn.d
index 8f0badf..8cb3d64 100644
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -21,34 +21,40 @@ Disassembly of section .text:
 [^:]+: R_RISCV_JAL[	]+target
 [^:]+:[ 	]+fddff56f[ 	]+jal[ 	]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[	]+target
-[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4
 [^:]+:[ 	]+852e[ 	]+mv[ 	]+a0,a1
+[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4
 [^:]+:[ 	]+002c[ 	]+addi[ 	]+a1,sp,8
-[^:]+:[ 	]+d9e9[ 	]+beqz[ 	]+a1,0 \<target\>
+[^:]+:[ 	]+c0aa[ 	]+sw[ 	]+a0,64\(sp\)
+[^:]+:[ 	]+41a8[ 	]+lw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+c1a8[ 	]+sw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+d5f1[ 	]+beqz[ 	]+a1,0 \<target\>
 [^:]+: R_RISCV_RVC_BRANCH[	]+target
-[^:]+:[ 	]+bfc1[ 	]+j[ 	]+0 \<target\>
+[^:]+:[ 	]+b7e9[ 	]+j[ 	]+0 \<target\>
 [^:]+: R_RISCV_RVC_JUMP[	]+target
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+00d58513[ 	]+addi[ 	]+a0,a1,13
 [^:]+:[ 	]+00a58567[ 	]+jalr[ 	]+a0,10\(a1\)
 [^:]+:[ 	]+00458503[ 	]+lb[ 	]+a0,4\(a1\)
-[^:]+:[ 	]+fab50fe3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+fab50ce3[ 	]+beq[ 	]+a0,a1,0 \<target\>
 [^:]+: R_RISCV_BRANCH[	]+target
-[^:]+:[ 	]+fab50de3[ 	]+beq[ 	]+a0,a1,0 \<target\>
+[^:]+:[ 	]+fab50ae3[ 	]+beq[ 	]+a0,a1,0 \<target\>
 [^:]+: R_RISCV_BRANCH[	]+target
 [^:]+:[ 	]+00a58223[ 	]+sb[ 	]+a0,4\(a1\)
 [^:]+:[ 	]+00fff537[ 	]+lui[ 	]+a0,0xfff
-[^:]+:[ 	]+fafff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+fa9ff56f[ 	]+jal[ 	]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[	]+target
-[^:]+:[ 	]+fabff56f[ 	]+jal[ 	]+a0,0 \<target\>
+[^:]+:[ 	]+fa5ff56f[ 	]+jal[ 	]+a0,0 \<target\>
 [^:]+: R_RISCV_JAL[	]+target
-[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4
 [^:]+:[ 	]+852e[ 	]+mv[ 	]+a0,a1
+[^:]+:[ 	]+0511[ 	]+addi[ 	]+a0,a0,4
 [^:]+:[ 	]+002c[ 	]+addi[ 	]+a1,sp,8
+[^:]+:[ 	]+c0aa[ 	]+sw[ 	]+a0,64\(sp\)
+[^:]+:[ 	]+41a8[ 	]+lw[ 	]+a0,64\(a1\)
+[^:]+:[ 	]+c1a8[ 	]+sw[ 	]+a0,64\(a1\)
 [^:]+:[ 	]+8d6d[ 	]+and[ 	]+a0,a0,a1
-[^:]+:[ 	]+ddd9[ 	]+beqz[ 	]+a1,0 \<target\>
+[^:]+:[ 	]+d9c9[ 	]+beqz[ 	]+a1,0 \<target\>
 [^:]+: R_RISCV_RVC_BRANCH[	]+target
-[^:]+:[ 	]+bf71[ 	]+j[ 	]+0 \<target\>
+[^:]+:[ 	]+bf41[ 	]+j[ 	]+0 \<target\>
 [^:]+: R_RISCV_RVC_JUMP[	]+target
 [^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
 [^:]+:[ 	]+68c58543[ 	]+fmadd.s[ 	]+fa0,fa1,fa2,fa3,rne
diff --git a/gas/testsuite/gas/riscv/insn.s b/gas/testsuite/gas/riscv/insn.s
index 6c08f49..937ad11 100644
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -10,11 +10,14 @@ target:
 	.insn uj 0x6f, a0, target
 	.insn j  0x6f, a0, target
 
-	.insn ci 0x1, 0x0, a0, 4
-	.insn cr 0x2, 0x8, a0, a1
+	.insn cr  0x2, 0x8, a0, a1
+	.insn ci  0x1, 0x0, a0, 4
 	.insn ciw 0x0, 0x0, a1, 1
-	.insn cb 0x1, 0x6, a1, target
-	.insn cj 0x1, 0x5, target
+	.insn css 0x2, 0x6, a0, 1
+	.insn cl  0x0, 0x2, a0, 1(a1)
+	.insn cs  0x0, 0x6, a0, 1(a1)
+	.insn cb  0x1, 0x6, a1, target
+	.insn cj  0x1, 0x5, target
 
 	.insn r  OP,  0,  0, a0, a1, a2
 	.insn i  OP_IMM,  0, a0, a1, 13
@@ -27,12 +30,15 @@ target:
 	.insn uj JAL, a0, target
 	.insn j  JAL, a0, target
 
-	.insn ci C1, 0x0, a0, 4
-	.insn cr C2, 0x8, a0, a1
+	.insn cr  C2, 0x8, a0, a1
+	.insn ci  C1, 0x0, a0, 4
 	.insn ciw C0, 0x0, a1, 1
-	.insn ca C1, 0x23, 0x3, a0, a1
-	.insn cb C1, 0x6, a1, target
-	.insn cj C1, 0x5, target
+	.insn css C2, 0x6, a0, 1
+	.insn cl  C0, 0x2, a0, 1(a1)
+	.insn cs  C0, 0x6, a0, 1(a1)
+	.insn ca  C1, 0x23, 0x3, a0, a1
+	.insn cb  C1, 0x6, a1, target
+	.insn cj  C1, 0x5, target
 
 	.insn r  MADD, 0, 0, a0, a1, a2, a3
 	.insn r4 MADD, 0, 0, a0, a1, a2, a3