| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-06-21 | x86: optimize {,V}PEXTR{D,Q} with immediate of 0 | Jan Beulich | 1 | -0/+38 |
| 2024-06-21 | x86: optimize left-shift-by-1 | Jan Beulich | 1 | -0/+79 |
| 2024-06-21 | x86: %riz, %rip, and %eip don't require REX | Jan Beulich | 1 | -2/+2 |
| 2024-06-21 | x86: don't suppress errors when optimizing | Jan Beulich | 1 | -1/+16 |
| 2024-06-18 | Support APX CCMP and CTEST | Cui, Lili | 1 | -1/+145 |
| 2024-06-10 | x86/APX: convert ZU to operand constraint | Jan Beulich | 1 | -1/+5 |
| 2024-05-31 | x86: reduce check_{byte,word,long,qword}_reg() overhead | Jan Beulich | 1 | -4/+15 |
| 2024-05-29 | x86/Intel: warn about undue mnemonic suffixes | Jan Beulich | 1 | -0/+13 |
| 2024-05-29 | x86/Intel: SHLD/SHRD have dual meaning | Jan Beulich | 1 | -2/+5 |
| 2024-05-24 | x86: simplify VexVVVV_SRC2 handling for the XOP case | Jan Beulich | 1 | -9/+5 |
| 2024-05-24 | x86: simplify / consolidate check_{word,long,qword}_reg() | Jan Beulich | 1 | -16/+4 |
| 2024-05-24 | x86: correct VCVT{,U}SI2SD | Jan Beulich | 1 | -5/+47 |
| 2024-05-22 | Support APX zero-upper | Cui, Lili | 1 | -2/+3 |
| 2024-05-22 | X86: Remove "i.rex" to eliminate extra conditional branch | Cui, Lili | 1 | -1/+1 |
| 2024-05-22 | Add check for 8-bit old registers in EVEX format | Cui, Lili | 1 | -3/+4 |
| 2024-05-22 | x86: Split REX/REX2 old registers judgment. | Cui, Lili | 1 | -16/+14 |
| 2024-05-06 | x86: Drop using extension_opcode to encode vvvv register | Cui, Lili | 1 | -6/+3 |
| 2024-05-06 | x86: Drop SwapSources | Cui, Lili | 1 | -8/+11 |
| 2024-05-06 | x86: Use vexvvvv as the switch state to encode the vvvv register | Cui, Lili | 1 | -15/+17 |
| 2024-05-03 | x86/APX: extend SSE2AVX coverage | Jan Beulich | 1 | -2/+7 |
| 2024-04-22 | x86/APX: Add invalid check for APX EVEX.X4. | Cui, Lili | 1 | -1/+4 |
| 2024-04-16 | x86: Fix a memory leak in md_assemble | H.J. Lu | 1 | -5/+8 |
| 2024-04-10 | x86-64: Use long NOPs for Intel Core processors | H.J. Lu | 1 | -5/+35 |
| 2024-04-07 | Support APX NF | Cui, Lili | 1 | -4/+31 |
| 2024-04-03 | x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4 | Cui, Lili | 1 | -7/+0 |
| 2024-03-28 | x86/SSE2AVX: move checking | Jan Beulich | 1 | -11/+10 |
| 2024-03-28 | x86/SSE2AVX: respect prefixes | Jan Beulich | 1 | -2/+3 |
| 2024-03-22 | x86: fix Solaris testsuite failures | Jan Beulich | 1 | -6/+3 |
| 2024-03-15 | x86/APX: legacy promoted insns can't access %xmm16-%xmm31 | Jan Beulich | 1 | -0/+7 |
| 2024-03-11 | x86: KeyLocker insn interaction with -msse-check / .sse_check | Jan Beulich | 1 | -1/+2 |
| 2024-03-11 | x86/APX: permit wider than 4-bit immediates with V{EXTRACT,INSERT}{F,I}128 | Jan Beulich | 1 | -1/+3 |
| 2024-03-11 | x86: don't open-code REG_{SP,FP} | Jan Beulich | 1 | -2/+2 |
| 2024-03-08 | gas: Fix x86 build with GCC 6.4 | H.J. Lu | 1 | -1/+1 |
| 2024-03-01 | x86: adjust which Dwarf2 register numbers to use | Jan Beulich | 1 | -19/+4 |
| 2024-03-01 | x86/APX: honor -mevexwig= for byte-size insns | Jan Beulich | 1 | -0/+9 |
| 2024-03-01 | x86/APX: optimize certain XOR and SUB forms | Jan Beulich | 1 | -0/+28 |
| 2024-03-01 | x86/APX: correct .insn opcode space determination when REX2 is needed | Jan Beulich | 1 | -28/+33 |
| 2024-03-01 | x86/APX: respect {vex}/{vex3} | Jan Beulich | 1 | -38/+111 |
| 2024-02-23 | x86: rename vec_encoding and vex_encoding_* | Jan Beulich | 1 | -72/+72 |
| 2024-02-22 | Leak in i386_elf_section_change_hook | Alan Modra | 1 | -1/+1 |
| 2024-02-15 | x86: Display -msse-check= default as none | H.J. Lu | 1 | -1/+1 |
| 2024-02-09 | x86: change type of Dwarf2 register numbers in register table | Jan Beulich | 1 | -8/+6 |
| 2024-02-08 | x86-64: Add R_X86_64_CODE_6_GOTTPOFF | H.J. Lu | 1 | -22/+80 |
| 2024-02-06 | gas: x86: ginsn: handle sub-QWORD ALU with imm and MOV ops correctly | Indu Bhagat | 1 | -0/+23 |
| 2024-02-06 | x86: Warn .insn instruction with length > 15 bytes | H.J. Lu | 1 | -2/+8 |
| 2024-02-02 | x86: Disallow instructions with length > 15 bytes | H.J. Lu | 1 | -2/+2 |
| 2024-02-02 | x86: move Q-suffix-to-REX.W translation logic | Jan Beulich | 1 | -17/+20 |
| 2024-02-02 | x86: actually implement .noopt | Jan Beulich | 1 | -1/+14 |
| 2024-02-01 | gas: x86: ginsn: adjust ginsns for certain lea ops | Indu Bhagat | 1 | -65/+57 |
| 2024-01-26 | x86: make "-msyntax=intel -mnaked-reg" match ".intel_syntax noprefix" | Jan Beulich | 1 | -8/+15 |
