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| author | Cui, Lili <lili.cui@intel.com> | 2024-05-22 16:15:47 +0800 |
|---|---|---|
| committer | Cui, Lili <lili.cui@intel.com> | 2024-05-22 16:15:47 +0800 |
| commit | bbe8d019ed362251ce429585c091a97e19cd0db7 (patch) | |
| tree | 4380ce6e9ff5cecd9bf4f4042263f5228f385d34 /gas/config/tc-i386.c | |
| parent | b757e3c1acbec5173f5ca04eb0cc7cfad7c7cb7e (diff) | |
| download | binutils-bbe8d019ed362251ce429585c091a97e19cd0db7.zip binutils-bbe8d019ed362251ce429585c091a97e19cd0db7.tar.gz binutils-bbe8d019ed362251ce429585c091a97e19cd0db7.tar.bz2 | |
Support APX zero-upper
This patch is to enable ZU for IMUL (opcodes 0x69 and 0x6B) and SETcc.
Since the spec only recommends one form of setzu, I won't be adding
set<cc>reg32/reg64 support in this patch.
gas/ChangeLog:
* config/tc-i386.c (build_apx_evex_prefix): Handle ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64.exp: Added new tests for ZU.
* testsuite/gas/i386/x86-64-apx-zu-intel.d: New test.
* testsuite/gas/i386/x86-64-apx-zu-inval.l: Ditto.
* testsuite/gas/i386/x86-64-apx-zu-inval.s: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.d: Ditto.
* testsuite/gas/i386/x86-64-apx-zu.s: Ditto.
opcodes/ChangeLog:
* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_40 ~
PREFIX_EVEX_MAP4_4F.
* i386-dis-evex.h: Ditto.
* i386-dis.c (struct dis386): Add new micro 'ZU'.
(putop): Handle %ZU.
* i386-gen.c: Added ZU.
* i386-opc.h: Ditto.
* i386-opc.tbl: Added new templates to support ZU.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index cb3d464..a84e999 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4285,8 +4285,9 @@ build_apx_evex_prefix (void) i.vex.bytes[3] &= ~0x08; /* Encode the NDD bit of the instruction promoted from the legacy - space. */ - if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4) + space. ZU shares the same bit with NDD. */ + if ((i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4) + || i.tm.opcode_modifier.zu) i.vex.bytes[3] |= 0x10; /* Encode the NF bit. */ |