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| author | Jan Beulich <jbeulich@suse.com> | 2024-05-03 09:26:25 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-05-03 09:26:25 +0200 |
| commit | 24187fb9c0d06f8084dfbd138e0b8b40d28ea024 (patch) | |
| tree | 5efe7de99da99d98124329312a2c543032ef525b /gas/config/tc-i386.c | |
| parent | d125c4bbce8398819df573754c2bf1224a15ec06 (diff) | |
| download | binutils-24187fb9c0d06f8084dfbd138e0b8b40d28ea024.zip binutils-24187fb9c0d06f8084dfbd138e0b8b40d28ea024.tar.gz binutils-24187fb9c0d06f8084dfbd138e0b8b40d28ea024.tar.bz2 | |
x86/APX: extend SSE2AVX coverage
Legacy encoded SIMD insns are converted to AVX ones in that mode. When
eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
available; there are quite a few which can't be converted).
Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
sse3 template there needs dropping, to get the order right).
Note further that in a few cases, due to the use of templates, AVX512VL
is used when AVX512F would suffice. Since AVX10 is the main reference,
this shouldn't be too much of a problem.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index b037468..13da7a6 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4133,7 +4133,7 @@ build_evex_prefix (void) /* Check the REX.W bit and VEXW. */ if (i.tm.opcode_modifier.vexw == VEXWIG) w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; - else if (i.tm.opcode_modifier.vexw) + else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W)) w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; else w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; @@ -8281,7 +8281,12 @@ check_VecOperands (const insn_template *t) if ((is_cpu (t, CpuXOP) && t->operands == 5) || (t->opcode_space == SPACE_0F3A && (t->base_opcode | 3) == 0x0b - && is_cpu (t, CpuAPX_F))) + && (is_cpu (t, CpuAPX_F) + || (t->opcode_modifier.sse2avx && t->opcode_modifier.evex + && (!t->opcode_modifier.vex + || (i.encoding != encoding_default + && i.encoding != encoding_vex + && i.encoding != encoding_vex3)))))) { if (i.op[0].imms->X_op != O_constant || !fits_in_imm4 (i.op[0].imms->X_add_number)) |