index
:
rocket-tools/riscv-tests/env.git
master
priv-1.10
priv-1.9
riscv-test-env-sail
vectorless
Unnamed repository; edit this file 'description' to name the repository.
root
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
p
Age
Commit message (
Expand
)
Author
Files
Lines
2023-02-02
env: trap and page fault filter mechanism (#40)
deepak0414
1
-0
/
+2
2021-09-24
update riscv_arch.h to support QEMU (#31)
liweiwei90
1
-2
/
+3
2020-11-24
Replace sptbr with satp throughout
Gokturk Yuksek
1
-1
/
+1
2020-10-14
unconditionally clear mie register
Sandeep Rajendran
1
-1
/
+1
2020-04-14
encoding: add new VCSR for vector 0.9
Chih-Min Chao
1
-1
/
+2
2020-03-04
Initialize x registers in p, pm, pt rather than just v (#21)
Andrew Waterman
1
-1
/
+35
2020-02-24
Fix #17 (#18)
Paul Donahue
1
-2
/
+0
2019-11-28
rvv: add mstatus.vs definition and initial mcaro
Chih-Min Chao
1
-0
/
+16
2019-11-28
fill exit syscall information to make semihosting work
Chih-Min Chao
1
-0
/
+4
2018-09-23
Avoid writing reserved values to pmpaddr CSR
Andrew Waterman
1
-1
/
+2
2017-11-27
Rename sptbr to satp
Andrew Waterman
1
-2
/
+2
2017-07-03
Fix physical load address for recent binutils
priv-1.10
Andrew Waterman
1
-3
/
+6
2017-05-01
Set ELF entry point correctly
Andrew Waterman
1
-0
/
+1
2017-03-30
New PMP encoding
Andrew Waterman
1
-1
/
+1
2017-03-27
Separate page faults from physical memory access exceptions
Andrew Waterman
1
-3
/
+3
2017-03-24
Clean up physical memory test init code
Andrew Waterman
1
-5
/
+20
2017-03-24
Avoid misa in physical memory tests
Andrew Waterman
1
-2
/
+2
2017-03-23
Rely on assembler to provide PMP CSRs
Andrew Waterman
1
-2
/
+2
2017-03-21
Use gp for TESTNUM, so compiled C code won't touch it
Andrew Waterman
1
-1
/
+1
2017-03-21
Set up PMP if present
Andrew Waterman
1
-3
/
+6
2017-03-09
WIP on priv-1.10
Andrew Waterman
1
-5
/
+8
2017-03-02
Check XLEN only after initializing mtvec
Andrew Waterman
1
-1
/
+1
2016-12-06
avoid non-standard predefined macros
Andrew Waterman
1
-1
/
+1
2016-08-15
add ALIGN after .tohost to prevent placing MMIO and data on same page (#3)
Sagar Karandikar
1
-1
/
+1
2016-07-11
Align mtvec to support RVC
Andrew Waterman
1
-0
/
+1
2016-07-07
Delegate interrupts to supervisor for supervisor tests
Andrew Waterman
1
-0
/
+5
2016-05-25
Keep tohost/fromhost at deterministic address
Andrew Waterman
2
-1
/
+4
2016-05-02
Stop using mtohost/mfromhost registers
Andrew Waterman
1
-2
/
+7
2016-04-30
ERET -> xRET; change memory map
Andrew Waterman
2
-13
/
+17
2016-03-02
WIP on priv spec v1.9
Andrew Waterman
1
-5
/
+4
2016-02-28
WIP on priv spec v1.9
Andrew Waterman
2
-40
/
+35
2015-09-28
make sure TESTNUM is initialized
Howard Mao
1
-0
/
+1
2015-09-20
Remove Hwacha v3 support
Andrew Waterman
1
-27
/
+0
2015-07-17
don't pass fpu/vector tests when fpu/vector not present
Yunsup Lee
1
-10
/
+1
2015-06-23
Avoid "csrw stvec" if stvec_handler doesn't exist.
Christopher Celio
1
-1
/
+2
2015-05-19
Improve coverage of VM tests
Andrew Waterman
1
-2
/
+0
2015-05-11
Initialize FCSR
Andrew Waterman
1
-1
/
+1
2015-05-09
Update to privileged architecture version 1.7
Andrew Waterman
2
-69
/
+18
2015-04-03
Don't assume initial values of mstatus.ua/sa
Andrew Waterman
1
-5
/
+15
2015-03-30
Don't rely on mstatus.fs to test FPU presence
Andrew Waterman
1
-9
/
+11
2015-03-25
add mtvec_handler to machine traps from user land
Yunsup Lee
1
-11
/
+22
2015-03-24
Don't assume PRV1/2 and IE1/2 are reset
Andrew Waterman
1
-2
/
+4
2015-03-17
relay hwacha cause/aux to scause/sbadaddr
Yunsup Lee
1
-1
/
+11
2015-03-17
Merge [shm]call into ecall, [shm]ret into eret
Andrew Waterman
1
-7
/
+7
2015-03-16
clean up pt and vector environments
Yunsup Lee
1
-3
/
+17
2015-03-12
Use hcall instead of mcall
Andrew Waterman
1
-6
/
+6
2015-03-12
Update to new privileged spec
Andrew Waterman
2
-15
/
+77
2015-01-09
Add LICENSE
Andrew Waterman
1
-0
/
+2
2015-01-04
Avoid deprecated "b" pseudo-op; use "j" instead
Andrew Waterman
1
-2
/
+2
2014-03-03
need to modify status register *before* enabling interrupts
Yunsup Lee
1
-2
/
+2
[next]