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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-12 22:29:04 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-04-14 00:28:13 -0700 |
| commit | 48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7 (patch) | |
| tree | 5b8b5305dcbdda968c6f4bd10e3c1546a88509fd /p | |
| parent | 197385c3d5f6c1845fdc73e2290dba5f598be292 (diff) | |
| download | env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.zip env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.tar.gz env-48c6d7cfcad3a20640bfe1ec2247c26003a3b6b7.tar.bz2 | |
encoding: add new VCSR for vector 0.9
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'p')
| -rw-r--r-- | p/riscv_test.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 2b9aad3..88ca6c1 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -142,7 +142,8 @@ li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \ (MSTATUS_FS & (MSTATUS_FS >> 1)); \ csrs mstatus, a0; \ - csrwi fcsr, 0 + csrwi fcsr, 0; \ + csrwi vcsr, 0; #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ |