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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-04 19:17:43 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-04 19:17:43 -0800 |
| commit | 500b89fb41ae857f5a1a0d6df382812cfce0b82e (patch) | |
| tree | 52f6d28ad5df48ecdcd5bb150f3dfa855329e6b8 /p | |
| parent | b9e08296ee04836ea4529f24adad378da946b92f (diff) | |
| download | env-500b89fb41ae857f5a1a0d6df382812cfce0b82e.zip env-500b89fb41ae857f5a1a0d6df382812cfce0b82e.tar.gz env-500b89fb41ae857f5a1a0d6df382812cfce0b82e.tar.bz2 | |
Initialize x registers in p, pm, pt rather than just v (#21)
Diffstat (limited to 'p')
| -rw-r--r-- | p/riscv_test.h | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 0941172..2b9aad3 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -63,6 +63,39 @@ # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: #endif +#define INIT_XREG \ + li x1, 0; \ + li x2, 0; \ + li x3, 0; \ + li x4, 0; \ + li x5, 0; \ + li x6, 0; \ + li x7, 0; \ + li x8, 0; \ + li x9, 0; \ + li x10, 0; \ + li x11, 0; \ + li x12, 0; \ + li x13, 0; \ + li x14, 0; \ + li x15, 0; \ + li x16, 0; \ + li x17, 0; \ + li x18, 0; \ + li x19, 0; \ + li x20, 0; \ + li x21, 0; \ + li x22, 0; \ + li x23, 0; \ + li x24, 0; \ + li x25, 0; \ + li x26, 0; \ + li x27, 0; \ + li x28, 0; \ + li x29, 0; \ + li x30, 0; \ + li x31, 0; + #define INIT_PMP \ la t0, 1f; \ csrw mtvec, t0; \ @@ -158,8 +191,9 @@ handle_exception: \ sw TESTNUM, tohost, t5; \ j write_tohost; \ reset_vector: \ + INIT_XREG; \ RISCV_MULTICORE_DISABLE; \ - INIT_SATP; \ + INIT_SATP; \ INIT_PMP; \ DELEGATE_NO_TRAPS; \ li TESTNUM, 0; \ |