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riscv_test.h
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Author
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2015-07-17
don't pass fpu/vector tests when fpu/vector not present
Yunsup Lee
1
-10
/
+1
2015-06-23
Avoid "csrw stvec" if stvec_handler doesn't exist.
Christopher Celio
1
-1
/
+2
2015-05-19
Improve coverage of VM tests
Andrew Waterman
1
-2
/
+0
2015-05-11
Initialize FCSR
Andrew Waterman
1
-1
/
+1
2015-05-09
Update to privileged architecture version 1.7
Andrew Waterman
1
-32
/
+13
2015-04-03
Don't assume initial values of mstatus.ua/sa
Andrew Waterman
1
-5
/
+15
2015-03-30
Don't rely on mstatus.fs to test FPU presence
Andrew Waterman
1
-9
/
+11
2015-03-25
add mtvec_handler to machine traps from user land
Yunsup Lee
1
-11
/
+22
2015-03-24
Don't assume PRV1/2 and IE1/2 are reset
Andrew Waterman
1
-2
/
+4
2015-03-17
relay hwacha cause/aux to scause/sbadaddr
Yunsup Lee
1
-1
/
+11
2015-03-17
Merge [shm]call into ecall, [shm]ret into eret
Andrew Waterman
1
-7
/
+7
2015-03-16
clean up pt and vector environments
Yunsup Lee
1
-3
/
+17
2015-03-12
Use hcall instead of mcall
Andrew Waterman
1
-6
/
+6
2015-03-12
Update to new privileged spec
Andrew Waterman
1
-14
/
+76
2015-01-09
Add LICENSE
Andrew Waterman
1
-0
/
+2
2015-01-04
Avoid deprecated "b" pseudo-op; use "j" instead
Andrew Waterman
1
-2
/
+2
2014-03-03
need to modify status register *before* enabling interrupts
Yunsup Lee
1
-2
/
+2
2014-02-25
make physical timer env work again
Yunsup Lee
1
-0
/
+2
2014-01-31
Support RV32S tests
Andrew Waterman
1
-0
/
+5
2014-01-31
Use TESTNUM instead of x28 directly
Andrew Waterman
1
-7
/
+5
2014-01-16
Source test failure value from correct register
Andrew Waterman
1
-4
/
+4
2013-11-24
Update to new privileged mode
Andrew Waterman
1
-17
/
+20
2013-11-13
split out envs from riscv-tests
Yunsup Lee
1
-0
/
+117