rocket-tools/riscv-tests/env.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
master	Support setting V-env LFSR bits with a compiler flag (#43)	Jerry Zhao	10 months
priv-1.10	Fix physical load address for recent binutils	Andrew Waterman	7 years
priv-1.9	Support RV32 virtual memory tests	Andrew Waterman	8 years
riscv-test-env-sail	created a branch for the sail-riscv testing env	William McSpaddden	4 weeks
vectorless	disable vector trap handling	Howard Mao	9 years


Age	Commit message	Author	Files	Lines
2015-11-17	disable vector trap handlingvectorless	Howard Mao	2	-23/+23
2015-07-17	don't pass fpu/vector tests when fpu/vector not present	Yunsup Lee	1	-10/+1
2015-07-06	Coherence torture test for VM tests	Andrew Waterman	1	-1/+24
2015-07-05	New M-mode timers; don't use sscratch in M-mode	Andrew Waterman	2	-50/+78
2015-06-23	Avoid "csrw stvec" if stvec_handler doesn't exist.	Christopher Celio	1	-1/+2
2015-05-19	Improve coverage of VM tests	Andrew Waterman	4	-46/+89
2015-05-11	Initialize FCSR	Andrew Waterman	1	-1/+1
2015-05-11	Fix VM, MIP encoding	Andrew Waterman	1	-6/+6
2015-05-09	Update to privileged architecture version 1.7	Andrew Waterman	9	-320/+193
2015-04-03	Rename VM_SV43 to VM_SV39	Andrew Waterman	2	-5/+7
[...]