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AgeCommit message (Expand)AuthorFilesLines
2015-11-17disable vector trap handlingvectorlessHoward Mao2-23/+23
2015-07-17don't pass fpu/vector tests when fpu/vector not presentYunsup Lee1-10/+1
2015-07-06Coherence torture test for VM testsAndrew Waterman1-1/+24
2015-07-05New M-mode timers; don't use sscratch in M-modeAndrew Waterman2-50/+78
2015-06-23Avoid "csrw stvec" if stvec_handler doesn't exist.Christopher Celio1-1/+2
2015-05-19Improve coverage of VM testsAndrew Waterman4-46/+89
2015-05-11Initialize FCSRAndrew Waterman1-1/+1
2015-05-11Fix VM, MIP encodingAndrew Waterman1-6/+6
2015-05-09Update to privileged architecture version 1.7Andrew Waterman9-320/+193
2015-04-03Rename VM_SV43 to VM_SV39Andrew Waterman2-5/+7
2015-04-03Don't assume initial values of mstatus.ua/saAndrew Waterman1-5/+15
2015-03-30Don't rely on mstatus.fs to test FPU presenceAndrew Waterman1-9/+11
2015-03-27New virtual memory implementation (Sv39)Andrew Waterman3-435/+519
2015-03-25add mtvec_handler to machine traps from user landYunsup Lee1-11/+22
2015-03-24Don't assume PRV1/2 and IE1/2 are resetAndrew Waterman1-2/+4
2015-03-17relay hwacha cause/aux to scause/sbadaddrYunsup Lee1-1/+11
2015-03-17change hwacha cause to follow risc-v causeYunsup Lee1-12/+14
2015-03-17Merge [shm]call into ecall, [shm]ret into eretAndrew Waterman5-36/+25
2015-03-16clean up pt and vector environmentsYunsup Lee6-175/+166
2015-03-14Check referenced/dirty bitsAndrew Waterman1-1/+7
2015-03-12Use hcall instead of mcallAndrew Waterman2-12/+17
2015-03-12Update to new privileged specAndrew Waterman7-300/+381
2015-03-12Fix include guardAlbert Ou1-1/+1
2015-01-09Add LICENSEAndrew Waterman7-0/+36
2015-01-04Avoid deprecated "b" pseudo-op; use "j" insteadAndrew Waterman2-5/+5
2014-11-25use new calling conventionAndrew Waterman2-23/+22
2014-11-22Revert "Enable support for the four custom instructions"Yunsup Lee1-72/+0
2014-11-06Improve VM env debug messagesAndrew Waterman1-6/+6
2014-10-24Merge pull request #1 from arunthomas/custom_instYunsup Lee1-0/+72
2014-10-23Enable support for the four custom instructionsArun Thomas1-0/+72
2014-04-03Sync encoding.h with opcodesStephen Twigg1-43/+61
2014-03-03need to modify status register *before* enabling interruptsYunsup Lee1-2/+2
2014-03-02Renumber uarch CSRs into custom CSR spaceYunsup Lee1-16/+16
2014-02-27enable interrupts *after* setting the evec registerYunsup Lee1-1/+1
2014-02-25make physical timer env work againYunsup Lee2-23/+47
2014-02-06fix recursive interrupts, and more improvements to codeYunsup Lee3-15/+29
2014-02-06Improve trap entry codeAndrew Waterman3-35/+23
2014-02-06Update CSRsAndrew Waterman1-48/+48
2014-02-06Update CSRsAndrew Waterman1-13/+96
2014-02-06fix vector exceptions on rocketYunsup Lee2-24/+15
2014-01-31Support RV32S testsAndrew Waterman1-0/+5
2014-01-31Use TESTNUM instead of x28 directlyAndrew Waterman2-29/+19
2014-01-20Update encoding.h to reflect JALR, RDCYCLE changesQuan Nguyen1-24/+24
2014-01-16Source test failure value from correct registerAndrew Waterman1-4/+4
2014-01-13Assume pc-relative addressingAndrew Waterman2-26/+26
2013-11-25Fix SLLI encodingAndrew Waterman1-2/+4
2013-11-24Update to new privileged modeAndrew Waterman7-178/+691
2013-11-13split out envs from riscv-testsYunsup Lee12-0/+1200
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