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2023-05-01Update OpenOCD cfg files to new syntaxTim Newsome1-1/+1
We were using a variety of deprecated commands. The driving force behind this was the new way to use `expr{}` as the old way no longer works with mainline OpenOCD.
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv2-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv2-2/+4
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
This file is wrong (the .cfg file isn't right) and not used by anything.
2017-08-28Make pylint happy.Tim Newsome1-1/+1
2017-08-28WIP multicore testing.Tim Newsome1-0/+2
2017-08-28Make the debug tests aware of multicore.Tim Newsome4-12/+24
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-10Give these sim targets a chance of passing.Tim Newsome2-3/+7
Also make sure vsim.log makes it into the generated log file.
2017-06-26Move target definition into individual files.Tim Newsome6-0/+90
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.