Move target definition into individual files.

Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.

Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.

6 files changed, 90 insertions, 0 deletions

diff --git a/debug/targets/SiFive/Freedom/E300.py b/debug/targets/SiFive/Freedom/E300.py
new file mode 100644
index 0000000..95ddcfd
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/E300.py
@@ -0,0 +1,9 @@
+import targets
+
+class E300(targets.Target):
+    xlen = 32
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
diff --git a/debug/targets/SiFive/Freedom/E300Sim.py b/debug/targets/SiFive/Freedom/E300Sim.py
new file mode 100644
index 0000000..e98c5b9
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/E300Sim.py
@@ -0,0 +1,13 @@
+import targets
+
+class E300Sim(targets.Target):
+    xlen = 32
+    timeout_sec = 6000
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
+
+    def target(self):
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)
diff --git a/debug/targets/SiFive/Freedom/Freedom.cfg b/debug/targets/SiFive/Freedom/Freedom.cfg
new file mode 100644
index 0000000..8947bf5
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/Freedom.cfg
@@ -0,0 +1,14 @@
+adapter_khz     10000
+
+source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+
+init
+
+halt
+echo "Ready for Remote Connections"
diff --git a/debug/targets/SiFive/Freedom/Freedom.lds b/debug/targets/SiFive/Freedom/Freedom.lds
new file mode 100644
index 0000000..1e0645a
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/Freedom.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/SiFive/Freedom/U500.py b/debug/targets/SiFive/Freedom/U500.py
new file mode 100644
index 0000000..c22aa4c
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/U500.py
@@ -0,0 +1,9 @@
+import targets
+
+class U500(targets.Target):
+    xlen = 64
+    ram = 0x80000000
+    ram_size = 16 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
diff --git a/debug/targets/SiFive/Freedom/U500Sim.py b/debug/targets/SiFive/Freedom/U500Sim.py
new file mode 100644
index 0000000..7648960
--- /dev/null
+++ b/debug/targets/SiFive/Freedom/U500Sim.py
@@ -0,0 +1,11 @@
+class U500Sim(Target):
+    xlen = 64
+    timeout_sec = 6000
+    ram = 0x80000000
+    ram_size = 256 * 1024 * 1024
+    instruction_hardware_breakpoint_count = 2
+    openocd_config_path = "Freedom.cfg"
+    link_script_path = "Freedom.lds"
+
+    def target(self):
+        return testlib.VcsSim(sim_cmd=self.sim_cmd, debug=False)