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AgeCommit message (Expand)AuthorFilesLines
2024-04-17debug: Fix nonexistent trigger registers trap handle in entry.Szilong1-1/+2
2024-02-02Add virtual memory synchronization after completing the page tablesliangzhen1-0/+1
2023-10-16Make CLINT address configurableliangzhen2-3/+9
2023-01-06debug: Tweak interrupt.c, so a test can run to exit()Tim Newsome1-1/+4
2022-12-29debug: Add etrigger test.Tim Newsome1-1/+1
2022-12-14debug: Remove unnecessary exit() functions. (#437)Tim Newsome1-0/+2
2022-12-01debug: Park unused harts with a cease instruction. (#434)Tim Newsome1-0/+12
2022-12-01Share exit() among more tests. (#433)Tim Newsome1-1/+1
2022-11-10SvNNTest needs 32KB of RAM. (#428)Tim Newsome1-1/+1
2022-11-04Make MulticoreRegTest work with real hardware.Tim Newsome1-1/+1
2022-10-26Specify trigger type=2 in trigger.S (#425)YenHaoChen1-2/+3
2022-06-08Test semihosting_fileioTim Newsome1-1/+3
2022-04-25Add EbreakTest. (#380)Tim Newsome1-0/+31
2021-11-29Fix TranslateTests. (#365)Tim Newsome1-3/+5
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome1-0/+2
2020-06-25Create a more sophisticated vector test (#284)Tim Newsome1-0/+159
2020-05-26Test semihosting calls (#280)Tim Newsome2-0/+155
2020-03-26Improve address translation tests (#261)Tim Newsome1-4/+16
2020-02-11Generate very different values on different harts. (#238)Tim Newsome1-0/+1
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome5-13/+182
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome2-4/+13
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome2-17/+18
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome1-0/+17
2018-11-12Simpler/more idiomatic way to keep string on stackTim Newsome1-4/+1
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome1-1/+1
2018-10-29Tweak debug tests to run out of flash.Tim Newsome2-1/+5
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome1-1/+1
2018-10-03Added tests for hw and sw watchpointscgsfv1-0/+17
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-04-27debug: add missing align directive on trap_entrytrap_entry_align-1Megan Wachs1-0/+1
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome1-10/+3
2017-11-27Rename sbadaddr to satpAndrew Waterman1-3/+3
2017-09-19Merge pull request #76 from riscv/multicoreTim Newsome2-13/+20
2017-09-19Forgot to commit this earlier.Tim Newsome1-0/+20
2017-09-18Add interrupts to MulticoreRunHaltStepiTest.Tim Newsome2-13/+20
2017-09-14Test debugging code with interrupts.Tim Newsome3-4/+34
2017-09-01Add some infrastructure for multicore tests.Tim Newsome2-8/+30
2017-08-28Forgot to add this file.Tim Newsome1-0/+81
2017-08-28WIP multicore testing.Tim Newsome1-7/+36
2017-08-28Make the debug tests aware of multicore.Tim Newsome2-12/+7
2017-07-20Add back code to clean up triggers in entry.STim Newsome1-0/+9
2017-07-03Don't clear triggers during execution.Tim Newsome1-9/+0
2017-06-27Tolerate missing misa register.Tim Newsome1-1/+7
2017-06-22Add basic multicore test.Tim Newsome1-33/+36
2017-06-20Smoketest multicore.Tim Newsome2-9/+40
2017-06-15Test 64-bit addressing.Tim Newsome2-9/+4
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt1-0/+0
2017-05-16Link in encoding.h instead of providing a path to itPalmer Dabbelt5-4/+5
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops (...Megan Wachs2-0/+14
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