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| author | Tim Newsome <tim@sifive.com> | 2017-06-27 10:53:16 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-06-27 10:53:16 -0700 |
| commit | 0bca79a33e902a7c43626ef89c51ecb9efd2125e (patch) | |
| tree | 4c4feaa1e1172d08734a53d7ade689bccb0b9505 /debug/programs | |
| parent | a0d927de2db60e20cd05ea245aa01f85aa99db94 (diff) | |
| download | riscv-tests-0bca79a33e902a7c43626ef89c51ecb9efd2125e.zip riscv-tests-0bca79a33e902a7c43626ef89c51ecb9efd2125e.tar.gz riscv-tests-0bca79a33e902a7c43626ef89c51ecb9efd2125e.tar.bz2 | |
Tolerate missing misa register.
At least in the test programs. There are other places where this causes
trouble as well.
Diffstat (limited to 'debug/programs')
| -rwxr-xr-x | debug/programs/entry.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/debug/programs/entry.S b/debug/programs/entry.S index c9e319c..ff8ae30 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -27,7 +27,9 @@ trap_vector: j trap_entry handle_reset: - la t0, trap_entry + // If misa doesn't exist (or is following an old spec where it has a + // different number), skip the next block. + la t0, 3f csrw mtvec, t0 csrwi mstatus, 0 @@ -48,6 +50,10 @@ handle_reset: csrwi medeleg, 0 2: csrwi mie, 0 +3: + la t0, trap_entry + csrw mtvec, t0 + csrwi mstatus, 0 # initialize global pointer .option push |