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| author | Tim Newsome <tim@sifive.com> | 2022-11-04 10:43:44 -0700 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-11-04 10:55:53 -0700 |
| commit | 0d690752517d82e6ce823ea20d2f4d95f535728f (patch) | |
| tree | 9849d4d4cc701df2e991aab961a061cc34b8892e /debug/programs | |
| parent | 99bf42aeba0719be2b575acc2f8ae28c55d65204 (diff) | |
| download | riscv-tests-0d690752517d82e6ce823ea20d2f4d95f535728f.zip riscv-tests-0d690752517d82e6ce823ea20d2f4d95f535728f.tar.gz riscv-tests-0d690752517d82e6ce823ea20d2f4d95f535728f.tar.bz2 | |
Make MulticoreRegTest work with real hardware.
It would fail intermittently. We can't guarantee all harts resume
simultaneously. When we let multiple harts run to a breakpoint at the
end of the same loop, one is likely to get there first, and the second
won't make it.
To avoid this problem, run for a short amount of time instead of to a
breakpoint.
Diffstat (limited to 'debug/programs')
| -rw-r--r-- | debug/programs/infinite_loop.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/debug/programs/infinite_loop.S b/debug/programs/infinite_loop.S index 5cc377c..d13f366 100644 --- a/debug/programs/infinite_loop.S +++ b/debug/programs/infinite_loop.S @@ -41,4 +41,4 @@ main_post_csrr: addi x30, x29, 1 addi x31, x30, 1 main_end: - j main + j main_end |