| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2022-10-21 | Change memory address used in debug tests. (#422) | Tim Newsome | 2 | -1/+1 | |
| https://github.com/riscv-software-src/riscv-isa-sim/pull/889 put a UART at the address we were using in our 32-bit debug tests. | |||||
| 2021-04-13 | Add FreeRTOS smoke tests. (#333) | Tim Newsome | 3 | -0/+7 | |
| * Add FreeRTOS smoke tests. Make sure that OpenOCD can access all threads in a FreeRTOS binary on single-hart RV32 and RV64. * Also test `-rtos FreeRTOS`. | |||||
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index : rocket-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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