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BranchCommit messageAuthorAge
ceasetest2Check basic debugging still works in CeaseMultiTim Newsome19 months
debugAdd debug statement.Tim Newsome4 years
debug_disassembledebug: On failure, disassemble close instructions.Tim Newsome21 months
disable_unavailabledebug: Disable Unavailable tests.Tim Newsome8 months
masterChange DTM IDCODE from SiFive HiFive1's 0x10e31913 to Spike's 0xdeadbeef (#565)Tommy Murphy3 days
miscMake newer version of pylint happy.Tim Newsome5 years
python3Move to Python 3.Tim Newsome5 years
riscv-tests-sailremoved the env/ directory, which was a submodule dir. replaced at a higher l...William McSpaddden4 weeks
tmptmpAndrew Waterman4 years
trigger_priorityRemove ineffective tests.Tim Newsome2 years
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AgeCommit messageAuthorFilesLines
2018-04-19Delete E300Sim.pydebug-delete-simMegan Wachs1-17/+0
2018-04-16Merge pull request #123 from riscv/gdb_timeoutTim Newsome2-14/+18
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome2-14/+18
2018-04-09Fix #120: Instructions 'sll' are replaced with 'slli' in rv64ui/slli.S (#121)Andrei Tatarnikov1-3/+3
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome4-0/+6
2018-03-27Test debug authentication.Tim Newsome4-3/+19
2018-03-23Print log filename at the end of the log.Tim Newsome1-0/+1
2018-03-21Make misa.C test conform to Hauser proposalAndrew Waterman1-43/+10
2018-03-20Merge pull request #119 from rishikhan/masterPalmer Dabbelt1-2/+8
2018-03-19Update Makefile to allow for RISCV_PREFIX to be set by the configure --targetrishi1-2/+8
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