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2022-05-27Remove ineffective tests.trigger_priorityTim Newsome1-2/+0
2022-05-25Address trigger has higher priority than alignmentTim Newsome1-0/+46
2022-05-16V implies FD now. (#382)Tim Newsome1-3/+3
2022-04-25Add EbreakTest. (#380)Tim Newsome2-0/+62
2022-04-07Make download test data const. (#378)Tim Newsome1-2/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
2022-03-03With new OpenOCD, gdb prints thread info differently (#373)Tim Newsome1-1/+2
2022-03-03Add assert to MemorySampleTest. (#370)Tim Newsome1-0/+1
2022-02-09Debug test to check that stepping doesn't inappropriately switch to Thread 1 ...Greg Savin1-0/+21
2022-01-06Add gdb.interact() for debug tests. (#367)Tim Newsome1-0/+18
2021-11-29Fix TranslateTests. (#365)Tim Newsome2-5/+7
2021-11-12Set `riscv resume_order reversed`. (#363)Tim Newsome1-0/+2
2021-11-12Create DisconnectTest. (#364)Tim Newsome2-32/+53
2021-11-12Add timing output to DebugTurboStep. (#362)Tim Newsome1-1/+5
2021-10-05Remove slen. (#360)Tim Newsome4-22/+16
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
2021-07-19Bump envAndrew Waterman1-20/+0
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-07-19Debug tests: catch write to nonexistent trigger registers in entry.S (#348)Luke Wren1-0/+7
2021-06-29Update README.md (#342)mymatin1-1/+1
2021-06-08Tweaks for multispike. (#339)Tim Newsome3-9/+19
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-20Test multiple heterogeneous spike instances. (#338)Tim Newsome6-63/+70
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#...SLAMET RIANTO2-0/+2
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C...SLAMET RIANTO3-0/+52
2021-05-07Test daisy chained homogeneous spike instances. (#334)Tim Newsome9-40/+303
2021-04-13Add FreeRTOS smoke tests. (#333)Tim Newsome9-15/+103
2021-02-11Add early_applicable() to a few tests. (#325)Tim Newsome1-7/+8
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
2021-02-01Prevent GCC from pattern-matching the memset implementationAndrew Waterman1-1/+1
2021-01-25Smoketest that vl and vtype can be modified. (#320)Tim Newsome2-29/+12
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
2021-01-08Disable V extension when compiler doesn't support it. (#317)Tim Newsome1-2/+24
2021-01-07Park other harts in TranslateTest. (#313)Tim Newsome1-0/+1
2021-01-07Stop testing `-rtos riscv`. (#314)Tim Newsome2-23/+3
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
2020-12-31Make HiFiveUnleashed tests clean.Tim Newsome7-1/+14
2020-12-18Add test for new OpenOCD `riscv info` command. (#310)Tim Newsome1-0/+13
2020-12-18Revive and expand invalid read test. (#309)Tim Newsome1-12/+19
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
2020-12-14Add tests for memory sampling feature. (#300)Tim Newsome10-1/+104
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-10-15bump env (#298)Sandeep Rajendran1-14/+14
2020-10-08Expose registers on all harts in openocd cfgs (#297)Samuel Obuch2-4/+10
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